RISC-V CPU Verification & Test Generator Lead

Tenstorrent University Jobs; Santa Clara (CA); Hybrid; USD 180,000 - 240,000; Full time

Job summary

Tenstorrent is seeking a senior CPU verification lead to own test generator development and verification strategy for high‑performance out‑of‑order RISC‑V cores. The role involves shaping ISA and microarchitectural validation across pre‑ and post‑silicon stages, and guiding a 4–5 person team while staying hands‑on in implementation, debugging, and verification.

You will collaborate with DV, architecture, and software teams to build scalable stimulus and verification infrastructure, expanding

Qualifications

• 8+ years in CPU design verification, test generation, or related CPU validation work.
• Led development of test generators for x86, ARM, or RISC-V ISA environments.
• Understands CPU ISA behavior, privileged architecture, and high‑performance out‑of‑order microarchitecture.

Responsibilities

• Lead development of CPU core‑level test generators for high‑performance out‑of‑order RISC‑V cores.
• Own generator strategy, infrastructure, and methodology for ISA and microarchitectural verification in pre‑ and post‑silicon stages.
• Develop directed and randomized stimulus targeting architectural corner cases and complex CPU behavior.
• Support RISC‑V certification work, including test content, compliance flows, debug, and closure.
• Guide a small team of 4–5 engineers while remaining hands‑on with implementation, debug, and verification.

Skills

CPU verification

Test generation

Team leadership

Automation

Education

Bachelor's or higher in CS/EE

Job description

Tenstorrent is seeking a senior CPU verification lead to own test generator development and verification strategy for high‑performance out‑of‑order RISC‑V cores. The role involves shaping ISA and microarchitectural validation across pre‑ and post‑silicon stages, and guiding a 4–5 person team while staying hands‑on in implementation, debugging, and verification.

You will collaborate with DV, architecture, and software teams to build scalable stimulus and verification infrastructure, expanding