Senior Verification Engineer - High-Perf RISC-V Cores

Tenstorrent; United States; Remote; USD 140,000 - 210,000; Full time

Job summary

Tenstorrent is seeking a seasoned verification engineer to verify the next generation of high-performance RISC-V CPU cores. You will write test plans, architect test benches, and develop verification strategies and environments.

The ideal candidate has 6+ years in design verification for CPUs or complex digital designs, strong SystemVerilog/UVM expertise, CPU architecture knowledge, and proficiency in C/C++ or Python.

Qualifications

• 6+ years of experience in design verification for CPUs or complex digital designs.
• Strong experience with SystemVerilog, UVM, and CPU architecture.
• Proficiency in C/C++ or Python and collaboration skills.

Responsibilities

• Write test plans and architect test benches.
• Debug failures and drive issues to closure.

Skills

SystemVerilog

UVM

CPU architecture

C/C++

Python

Testbench development

Debugging

Job description

Tenstorrent is seeking a seasoned verification engineer to verify the next generation of high-performance RISC-V CPU cores. You will write test plans, architect test benches, and develop verification strategies and environments.

The ideal candidate has 6+ years in design verification for CPUs or complex digital designs, strong SystemVerilog/UVM expertise, CPU architecture knowledge, and proficiency in C/C++ or Python.