Ph.D. Intern – Analog, Mixed Signal & Circuit Design

Jobtailor; Santa Clara (CA); On-site; USD 50,000 - 70,000; Part time

Job summary

Jobtailor in Santa Clara, CA invites a PhD student in Electrical Engineering to join our analog/mixed-signal design team. Design, simulate, and verify blocks across the full design flow—from architecture and schematic to silicon bring‑up—in advanced CMOS FinFET processes.

Use Cadence and MATLAB for simulation; collaborate with layout engineers; participate in design reviews; and present results. You will also follow a structured analog design curriculum alongside other PhD interns.

Qualifications

• Enrolled in a Ph.D. program with a focus on analog, mixed-signal, or RF circuit design.
• Hands-on experience designing/simulating analog blocks (PLL, SerDes, ADC/DAC, LDO, high-speed I/O).
• Strong transistor-level design fundamentals for advanced CMOS processes.

Responsibilities

• Design, simulate, and verify analog/mixed-signal blocks across the full design flow.
• Collaborate with layout engineers and iterate based on simulation and silicon feedback.
• Attend design reviews and present research framing and results to engineers.
• Participate in a structured analog design curriculum alongside other Ph.D. intern peers.

Skills

Analog Circuit Design

Mixed-Signal Circuit Design

Transistor-Level Circuit Design

High-Speed I/O Design

PLLs

SerDes Building Blocks

ADCs

DACs

LDOs

Device Physics

Education

Ph.D. in Electrical Engineering

Tools

Cadence

MATLAB

Spectre

Verilog-A

Job description

• Design, simulate, and verify analog and mixed-signal circuit blocks across the full design flow, from architecture and schematic through simulation, layout coordination, and silicon bring-up
• Work on production-grade IP including high-speed SerDes building blocks, Silicon Photonics driver and receiver circuits, ADC/DAC architectures, PLLs, clock distribution networks, LDOs, and other precision analog circuits in advanced CMOS FinFET processes
• Use Cadence and MATLAB throughout the project
• Collaborate directly with layout engineers to implement designs and iterate based on simulation and silicon feedback
• Attend and contribute to design reviews alongside the engineering team
• Present research framing and design results to engineers
• Participate in a structured analog design curriculum alongside Ph.D. intern peers

Requirements

• Currently enrolled in a Ph.D. program in Electrical Engineering or a related field, with a research focus in analog, mixed-signal, or RF circuit design
• Hands-on experience designing and simulating analog circuit blocks such as PLLs, SerDes building blocks, ADCs, DACs, LDOs, amplifiers, or high-speed I/O
• Strong fundamentals in transistor-level circuit design, including device physics, noise analysis, linearity, stability, and low-power techniques in advanced CMOS processes
• Ability to simulate and verify designs independently using Cadence Virtuoso and Spectre
• MATLAB or Python for system-level modeling is a plus
• Experience designing in FinFET process nodes (7nm, 5nm, 3nm, or equivalent) preferred
• Familiarity with high-speed serial link architectures, optical transceiver circuits, or Die-to-Die interconnect design preferred
• Exposure to layout-aware design, parasitic extraction, or post-layout simulation preferred
• Experience with behavioral modeling in Verilog-A or similar preferred
• Ability to communicate design decisions and tradeoffs clearly and present work to the engineering team
• Applicants must be eligible to access export-controlled information under applicable U.S. law; non-exempt applicants may be subject to export license review

Core Competencies

Demonstrates expertise in analog and mixed-signal circuit design, including proficiency in Cadence and MATLAB for simulation and verification. Strong understanding of advanced CMOS processes and hands-on experience with high-speed SerDes, ADCs, DACs, and PLLs.

Highest-signal resume keywords

• Analog Circuit Design
• Mixed-Signal Circuit Design
• Cadence Virtuoso
• FinFET Process Design
• Transistor-Level Circuit Design

Hard Skills

• Analog Circuit Design
• Mixed-Signal Circuit Design
• Transistor-Level Circuit Design
• High-Speed I/O Design
• PLLs
• SerDes Building Blocks
• ADCs
• DACs
• LDOs
• Device Physics

Soft Skills

• Communication
• Collaboration
• Presentation

Industry Keywords

• CMOS
• FinFET
• Silicon Photonics
• High-Speed Serial Link Architectures
• Die-to-Die Interconnect Design

Tools & Technologies

• Cadence
• MATLAB
• Spectre
• Verilog-A