Remote SI/PI Technical Leader - ASIC Packaging

Cisco Systems

Columbia (SC)

Hybrid

USD 214,000 - 310,000

Full time

6 days ago

Be an early applicant

Application generator

Don’t send a generic resume — generate a resume and cover letter tailored to this exact role.

Get past ATS filters

Job summary

Cisco Silicon One in San Jose, CA is seeking a seasoned Signal and Power Integrity Technical Leader to guide our packaging strategy and CI/PI across multiple platforms. You will define rules for ultra-high-speed signaling and mentor a skilled SI team, influencing both packaging and hardware teams.

The role emphasizes leadership in chip architecture discussions, 2.5D packaging, and collaborations to achieve performance and reliability goals.

Qualifications

Bachelor's degree in Electrical Engineering with 10+ years of signal/power integrity experience.
Experience with multiple high-speed ASIC tape-outs from a package perspective.
Expertise in 56G PAM4 and above, high-speed SerDes, channel modeling and BER prediction.
Hands-on lab experience with Keysight ADS, Ansys HFSS/EM flow, and Cadence APD for layout review.
Experience with SPICE.

Responsibilities

Lead ASIC packaging SI/PI team to define, design and verify packaging.
Develop design rules for ultra-high-speed signaling meeting power/performance/area goals.
Analyze substrate SI/PI and collaborate with layout to optimize interposer, substrate, and PCB.
Design and develop ASIC packages for high-volume release, including post-layout extraction.
Collaborate with system partners and vendors to resolve complex technical issues.