Remote Senior ASIC Design Engineer - AI/HPC Networking

Cornelis Networks, Inc.; San Jose (CA); Remote; USD 180,000 - 240,000; Full time

Job summary

Cornelis Networks is seeking Senior ASIC Design Engineers to advance world‑class SoCs for AI HPC interconnects. You will design RTL in Verilog/SystemVerilog for high‑speed data paths, and collaborate across hardware, firmware and software teams to validate and optimize performance at scale.

Ideal candidates have 8+ years in digital design, strong debugging skills, and experience with timing closure and physical design.

Qualifications

• 8+ years of post‑college experience in digital design.
• Experience in RTL design for high‑speed data paths or packet processing in ASICs.
• Familiarity with timing closure and modern physical design methodologies.
• Proven ability in system‑level debug and root cause analysis of technical issues.
• Strong verbal and written communication skills.

Responsibilities

• Implement RTL designs using Verilog/SystemVerilog for high‑speed data paths and packet processing.
• Collaborate with verification engineers to create block‑ and system‑level test plans.
• Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure.
• Support post‑silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues.
• Contribute to performance optimization and power‑aware design strategies for Host Fabric Interface subsystems.

Skills

Verbal communication

Written communication

Education

B.S./M.S. in Electrical/Computer Engineering

Tools

Verilog

SystemVerilog

Job description

Cornelis Networks is seeking Senior ASIC Design Engineers to advance world‑class SoCs for AI HPC interconnects. You will design RTL in Verilog/SystemVerilog for high‑speed data paths, and collaborate across hardware, firmware and software teams to validate and optimize performance at scale.

Ideal candidates have 8+ years in digital design, strong debugging skills, and experience with timing closure and physical design.