PCIe ASIC Design Engineer

Cornelis Networks; Austin (TX); On-site; USD 150,000 - 230,000; Full time

Benefits offered by this job

Equity

Bonus potential

Health benefits

401(k) with company match

Paid holidays

Open Time Off

Job summary

Cornelis Networks is hiring a Senior ASIC Design Engineer to lead PCIe controller integration into next-gen SoCs, driving IP bring-up and interconnect scalability. You will collaborate across architecture, verification, PD, and software teams to deliver robust PCIe subsystems.

The role emphasizes hands-on silicon bring-up, lab validation, and mentoring of junior engineers, with a strong focus on high-speed PCIe performance and protocol compliance. Remote-friendly in the U.S.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of industry experience in ASIC/SoC design with a focus on PCIe controller integration.
• Proven experience in silicon bring-up and debug of high-speed interfaces.
• Solid understanding of PCIe protocol stack (PHY, MAC, TLP, DLL), configuration space, and link training.
• Hands-on experience with PCIe verification environments, performance tuning, and power-aware design.
• Familiarity with PCIe compliance testing, simulation tools (e.g., VCS, Questa), and lab equipment (e.g., protocol analyzers, oscilloscopes).
• Strong scripting (Python, Perl, TCL) and debugging skills.
• Strong verbal and written communication skills.

Responsibilities

• Own end-to-end integration of PCIe IP into complex ASIC designs.
• Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
• Drive performance optimization efforts across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency.
• Contribute to system architecture and microarchitecture discussions with a focus on IO and interconnect scalability.
• Lead silicon bring-up and validation of PCIe links in the lab; work closely with board and firmware teams.
• Debug functional and performance issues at RTL, gate-level, and silicon.
• Ensure compliance with PCIe specifications and participate in interoperability testing where needed.
• Provide mentorship to junior engineers and help define PCIe subsystem development best practices.
• Good understanding of high-bandwidth, low-latency connectivity for high-performance compute platforms

Skills

ASIC/SoC design

PCIe controller integration

PCIe protocol

High-speed interfaces

Python/Perl/TCL

RTL/Debugging

Verilog

Lab equipment

PCIe verification

Debugging

Education

Electrical/Computer Eng degree

Tools

VCS/Questa

Emulation platforms (ZeBu, Palladium, HAPS)

Job description

At Cornelis we’re building the future of AI and HPC networking with an AI-first approach to silicon and software development. We’re seeking engineers who are energized by working on cutting-edge ASIC design and distributed software systems, and who are motivated to push the boundaries on how AI can transform everything from chip architecture to system performance at scale.

Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions.

We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles.

Cornelis Networks is hiring a Senior ASIC Design Engineer to lead the design and integration of PCIe controllers into our next-generation SoCs. The ideal candidate will have deep expertise in PCI Express protocol (Gen4/Gen5/Gen6), integration into high performance ASICs, emulation and post silicon bring-up.

Key Responsibilities

• Own end-to-end integration of PCIe IP into complex ASIC designs.
• Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
• Drive performance optimization efforts across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency.
• Contribute to system architecture and microarchitecture discussions with a focus on IO and interconnect scalability.
• Lead silicon bring-up and validation of PCIe links in the lab; work closely with board and firmware teams.
• Debug functional and performance issues at RTL, gate-level, and silicon.
• Ensure compliance with PCIe specifications and participate in interoperability testing where needed.
• Provide mentorship to junior engineers and help define PCIe subsystem development best practices.
• Good understanding of high-bandwidth, low-latency connectivity for high-performance compute platforms

Minimum Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of industry experience in ASIC/SoC design with a focus on PCIe controller integration.
• Proven experience in silicon bring-up and debug of high-speed interfaces.
• Solid understanding of PCIe protocol stack (PHY, MAC, TLP, DLL), configuration space, and link training.
• Hands-on experience with PCIe verification environments, performance tuning, and power-aware design.
• Familiarity with PCIe compliance testing, simulation tools (e.g., VCS, Questa), and lab equipment (e.g., protocol analyzers, oscilloscopes).
• Strong scripting (Python, Perl, TCL) and debugging skills.
• Strong verbal and written communication skills.

Preferred Qualifications

• Experience with PCIe Gen5/Gen6 and advanced retimer or switch solutions.
• Exposure to CXL, CCIX, or other cache-coherent interconnects.
• Background in data center or AI/ML accelerator architectures.
• Experience with emulation and prototyping platforms (e.g., ZeBu, Palladium, HAPS) for PCIe subsystem validation.

Location: This is a remote position for employees residing within the United States.

We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry.

At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives.

In addition to your base pay, you’ll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave.

Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.