Remote Senior Digital IC Engineer RTL Design & Verification

Visibl Semiconductors Inc.; United States; Remote; USD 180,000 - 250,000; Full time

Job summary

Visibl Semiconductors is seeking a Senior Digital IC Engineer to own a substantial digital subsystem in a forthcoming mixed‑signal ASIC. You’ll collaborate with our CTO, analog lead and customer firmware engineers to own digital implementation, verification and synthesis handoff.

You’ll drive interfaces, RTL design, verification planning and a reproducible build-and-test flow while ensuring clean timing and integration.

Qualifications

• Own RTL design through tapeout and validation.
• Strong SystemVerilog RTL design and self-checking verification skills.
• Experience with synthesis and timing analysis.
• Ability to resolve hardware–firmware interface questions with engineers from other disciplines.

Responsibilities

• Requirements and interfaces: clarify expected behavior and document interfaces.
• Digital design: develop and refine RTL for control and configuration logic.
• Verification: create a verification plan, build testbenches and regressions.
• Implementation handoff: manage lint, clock/reset-domain crossing analysis, synthesis, timing constraints and timing analysis.

Skills

SystemVerilog RTL design

Self-checking verification

Synthesis

Static timing analysis

Timing constraints

Metastability handling

HW-FW interface questions

Independent work

Tools

ASIC tapeout

Job description

Visibl Semiconductors is seeking a Senior Digital IC Engineer to own a substantial digital subsystem in a forthcoming mixed‑signal ASIC. You’ll collaborate with our CTO, analog lead and customer firmware engineers to own digital implementation, verification and synthesis handoff.

You’ll drive interfaces, RTL design, verification planning and a reproducible build-and-test flow while ensuring clean timing and integration.