RTL/ASIC Engineer- Remote

YO IT Consulting; United States; On-site; USD 100,000 - 130,000; Full time

Job summary

YO IT Consulting is seeking a full-time RTL Design Engineer with 3-10 years of experience in digital RTL design. The ideal candidate will possess strong proficiency in Verilog/SystemVerilog and a solid understanding of digital design fundamentals. Responsibilities include working with ASIC design flows and writing clear design documentation. Remote work is available for candidates based in the USA and Canada.

Qualifications

• 3-10 years of experience in digital RTL design.
• Strong proficiency in Verilog / SystemVerilog.
• Understanding of digital design fundamentals needed.

Skills

RTL design experience

Proficiency in Verilog / SystemVerilog

Understanding of digital design fundamentals

Experience with ASIC design flows

Familiarity with EDA tools

Ability to write clear documentation

Collaboration skills

Debugging RTL issues

Job description

Commitment: Full-time preferred; high availability required (40 hours)

Duration: Target engagement of ~3+ months

Location: Remote, USA and Canada only

RTL Design Engineer

Qualifications

• 3-10 years of experience in digital RTL design
• Strong proficiency in Verilog / SystemVerilog
• Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols
• Experience with ASIC design flows: lint, synthesis, timing analysis, CDC, DFT-aware design
• Familiarity with common EDA tools for simulation, waveform debug, lint, CDC, synthesis, timing analysis
• Familiarity with leveraging LLM-based tools to accelerate chip design, RTL development, debug, documentation, or verification workflows
• Ability to write clear design documentation and communicate technical tradeoffs
• Experience debugging RTL issues using simulation logs and waveform viewers
• Strong collaboration skills across architecture, verification, and implementation teams

Preferred

• AMBA protocols (AXI, AHB, APB)
• Background in one or more of: CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect, low-power design
• Exposure to formal verification or SV/UVM-based design verification

Design Verification Engineer

Qualifications

• 3-10 years of experience in design verification
• Strong proficiency in SystemVerilog and UVM
• Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols
• Experience developing reusable verification components and testbench infrastructure
• Constrained-random verification, functional coverage, assertions (SVA), coverage closure
• Familiarity with EDA tools for simulation, waveform debug, coverage analysis, formal verification, regression management
• Familiarity with LLM-based tools to accelerate verification, debug, test generation, documentation, or coverage analysis
• Ability to write clear verification plans, debug reports, and technical documentation

Preferred

• AMBA protocols (AXI, AHB, APB)
• Background in one or more of: CPU, GPU / ML accelerator, networking, memory subsystem, PCIe / high-speed IO, SoC interconnect, low-power verification
• Reusable verification IP, scoreboards, reference models, coverage-driven regression flows