Remote DFT Architect for High-Speed CPU Cores

Tenstorrent; Santa Clara, Northern (CA, KY); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a senior DFT engineer to lead chip-level DFT strategy for high-speed CPU cores and multi-chiplet SIP designs. The role emphasizes testability, silicon debug, and signoff of DFT logic, with collaboration across RTL, PD, and verification teams.

The position is remote from the United States, offering exposure to global teams and complex silicon development, with compensation tied to experience and project scope.

Qualifications

• BS/MS/PhD in EE/CE/CS with 10+ years of DFT experience.
• Hands-on with DFT tools such as Synopsys and Siemens; TCL/Python scripting.
• Expertise in DFT planning, SoC silicon debug, formal verification, and DFT signoff.

Responsibilities

• Build and execute chip-level DFT strategies for high-speed CPU core designs and multi-chiplet SIPs.
• Implement and verify DFT features including scan chains, memory BIST, and JTAG.
• Partner with RTL, physical design, and verification to ensure testability throughout the flow.
• Script, automate, and analyze DFT flows using industry tools (ATPG, fault coverage).

Skills

DFT experience

TCL scripting

Python programming

Cross-functional collab

Risk assessment

Education

BS/MS/PhD in EE/CE/CS

Tools

Synopsys

Siemens

Job description

Tenstorrent is seeking a senior DFT engineer to lead chip-level DFT strategy for high-speed CPU cores and multi-chiplet SIP designs. The role emphasizes testability, silicon debug, and signoff of DFT logic, with collaboration across RTL, PD, and verification teams.

The position is remote from the United States, offering exposure to global teams and complex silicon development, with compensation tied to experience and project scope.