Remote ASIC Verification Engineer - Network/Ethernet

Tessolve

San Jose (CA)

Remote

USD 150,000 - 200,000

Full time

32 hours ago
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Job summary

Tessolve is seeking a senior ASIC Verification Engineer with Network/Ethernet expertise for San Jose, CA or REMOTE. The role emphasizes verification of Ethernet MAC/PHY, PCIe, TCP/IP, and related protocols within a full verification flow.

Candidates should have 10+ years of ASIC verification experience, strong SystemVerilog/UVM skills, and a proven ability to design modular, reusable testbenches and automated verification environments.

Qualifications

  • BS or MS in Electrical Engineering, Computer Science, or related field.
  • Minimum 10+ years of ASIC verification experience.
  • Strong understanding of ASIC verification fundamentals and industry standard methodologies.
  • Experience with Verilog/SystemVerilog, UVM, Python, TCL, C/C++.
  • Experience with the full verification flow, from spec to coverage analysis to gate level sim.
  • Debugging failures in simulation to root cause problems.
  • Self-motivated and able to work effectively both independently and in a team.
  • Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other protocols).
  • Digital signal processing filters and 3rd party IP (SerDes, controllers, processors, etc.).
  • Modular and reusable testbench architecture.
  • Design for re-use of pre and post silicon tests and infrastructure.
  • Automation of testbench creation, tests, regression, or EDA tools.

Skills

Networking
Ethernet
TCP/IP
PCIe
Debugging
Testbench architecture

Education

BS/MS in Electrical Engineering or Computer Science

Tools

Verilog/SystemVerilog
UVM
Python
TCL
C/C++

Job description

Tessolve is seeking a senior ASIC Verification Engineer with Network/Ethernet expertise for San Jose, CA or REMOTE. The role emphasizes verification of Ethernet MAC/PHY, PCIe, TCP/IP, and related protocols within a full verification flow.

Candidates should have 10+ years of ASIC verification experience, strong SystemVerilog/UVM skills, and a proven ability to design modular, reusable testbenches and automated verification environments.

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