Remote ASIC/SoC Design & Verification Engineer (Part-Time)

Weekday AI; United States; Remote; USD 96,000 - 138,000; Part time

Job summary

Weekday AI seeks experienced ASIC/SoC Design & Verification Engineers for a fully remote, part-time engagement. You will contribute RTL design, verification, and silicon implementation expertise to advance AI model capabilities. Ideal for engineers with tapeout experience and strong SystemVerilog skills.

Role requires 20–40 hours per week with flexible scheduling. Remote collaboration with a distributed team across the United States is expected, with weekly payments for completed work.

Qualifications

• Hands-on experience in ASIC and/or SoC design, functional verification, or digital hardware development.
• Strong proficiency in SystemVerilog and Verilog.
• Experience with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium, Siemens Questa, VC Formal, Verdi; open-source tools including Icarus Verilog, Verilator, Cocotb, Yosys, OpenROAD.

Responsibilities

• Design realistic chip architecture, RTL, debugging, and verification challenges based on real engineering experience.
• Develop reference solutions including RTL implementations, verification environments, testbenches, and supporting docs using Verilog/SystemVerilog.
• Evaluate AI-generated hardware solutions and provide detailed technical feedback.
• Analyze where AI models struggle with hardware concepts, debugging, verification strategies, and design trade-offs.
• Collaborate with hardware engineers to maintain consistency and high-quality standards across evaluation tasks.
• Help improve AI understanding of modern digital design methodologies, verification practices, and semiconductor workflows.

Skills

ASIC/SoC design

SystemVerilog

Verilog

RTL development

Functional verification

Remote work

Independent work

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

VC Formal

Verdi

Icarus Verilog

Verilator

Cocotb

Yosys

OpenROAD

Job description

Weekday AI seeks experienced ASIC/SoC Design & Verification Engineers for a fully remote, part-time engagement. You will contribute RTL design, verification, and silicon implementation expertise to advance AI model capabilities. Ideal for engineers with tapeout experience and strong SystemVerilog skills.

Role requires 20–40 hours per week with flexible scheduling. Remote collaboration with a distributed team across the United States is expected, with weekly payments for completed work.