ASIC/SoC Design & Verification Engineer

Weekday AI; United States; Remote; USD 96,000 - 138,000; Part time

Job summary

Weekday AI seeks experienced ASIC/SoC Design & Verification Engineers for a fully remote, part-time engagement. You will contribute RTL design, verification, and silicon implementation expertise to advance AI model capabilities. Ideal for engineers with tapeout experience and strong SystemVerilog skills.

Role requires 20–40 hours per week with flexible scheduling. Remote collaboration with a distributed team across the United States is expected, with weekly payments for completed work.

Qualifications

• Hands-on experience in ASIC and/or SoC design, functional verification, or digital hardware development.
• Strong proficiency in SystemVerilog and Verilog.
• Experience with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium, Siemens Questa, VC Formal, Verdi; open-source tools including Icarus Verilog, Verilator, Cocotb, Yosys, OpenROAD.

Responsibilities

• Design realistic chip architecture, RTL, debugging, and verification challenges based on real engineering experience.
• Develop reference solutions including RTL implementations, verification environments, testbenches, and supporting docs using Verilog/SystemVerilog.
• Evaluate AI-generated hardware solutions and provide detailed technical feedback.
• Analyze where AI models struggle with hardware concepts, debugging, verification strategies, and design trade-offs.
• Collaborate with hardware engineers to maintain consistency and high-quality standards across evaluation tasks.
• Help improve AI understanding of modern digital design methodologies, verification practices, and semiconductor workflows.

Skills

ASIC/SoC design

SystemVerilog

Verilog

RTL development

Functional verification

Remote work

Independent work

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

VC Formal

Verdi

Icarus Verilog

Verilator

Cocotb

Yosys

OpenROAD

Job description

This role is for one of our clients

Compensation: $70-$100 per hour

Join a cutting-edge AI initiative focused on advancing how next-generation AI systems understand real-world hardware engineering. We are seeking experienced ASIC and SoC Design & Verification Engineers to contribute their expertise in digital design, RTL development, functional verification, and silicon implementation to improve AI model capabilities.

Whether you're an early-career engineer, a PhD researcher, or a seasoned professional who has successfully taken chips through tapeout, this opportunity allows you to apply your practical engineering knowledge to help train and evaluate frontier AI systems.

This is a fully remote, part-time engagement requiring approximately 20–40 hours per week, depending on your availability.

Key Responsibilities

• Design realistic chip architecture, RTL, debugging, and verification challenges based on real engineering experience.
• Develop complete reference solutions, including RTL implementations, verification environments, testbenches, and supporting documentation using Verilog/SystemVerilog.
• Evaluate AI-generated hardware solutions, identify strengths and weaknesses, and provide detailed technical feedback.
• Analyze where AI models struggle with hardware engineering concepts, debugging, verification strategies, and design trade-offs.
• Collaborate with fellow hardware engineers to maintain consistency, technical accuracy, and high-quality engineering standards across all evaluation tasks.
• Help improve AI understanding of modern digital design methodologies, verification practices, and semiconductor development workflows.

Required Qualifications

• Hands-on experience in ASIC and/or SoC design, functional verification, or digital hardware development, preferably involving production silicon or tapeout projects.
• Strong proficiency in SystemVerilog and Verilog.
• Experience working with industry-standard EDA tools such as Synopsys VCS, Cadence Xcelium, Siemens Questa, VC Formal, Verdi, or equivalent open-source tools including Icarus Verilog, Verilator, Cocotb, Yosys, and OpenROAD.
• Strong understanding of system-level hardware concepts including interface protocols, clock-domain crossing (CDC), handshaking, backpressure, and multi-module data flow.
• Deep expertise in one or more of the following areas:
  • RTL Design and Microarchitecture
  • Functional Verification (UVM, SVA, Cocotb, testbench development)
  • IP Integration and SoC Bring-up (AXI, PCIe, DDR, NoC, ARM-based systems)
  • Formal Verification and Coverage Closure
  • Timing Closure, Synthesis, Power, Performance, and Area (PPA) Optimization
  • Analog/Mixed-Signal Design Verification
  • Hardware Specification Development and Technical Documentation
• Ability to commit 20–40 hours per week with reliable weekday availability.
• Strong written communication skills and the ability to work independently in a remote environment.

Preferred Qualifications

• Experience participating in AI model training, evaluation, data annotation, or technical benchmarking projects.
• Graduate research or industry experience in semiconductor design, verification, or computer architecture.
• Familiarity with modern AI-assisted engineering tools and automated hardware design workflows.
• Experience mentoring engineers or reviewing complex technical designs.

Why Join

• Help shape how advanced AI systems understand and solve real-world semiconductor engineering challenges.
• Apply your practical chip design and verification expertise to improve the next generation of AI models.
• Work alongside experienced hardware engineers, researchers, and AI specialists on high-impact projects.
• Enjoy the flexibility of a fully remote engagement with opportunities for continued collaboration based on performance.

Equal Opportunity

We are committed to creating an inclusive environment and welcome applications from qualified professionals of all backgrounds. Reasonable accommodations are available throughout the application and engagement process.

Contract & Engagement Details

• Independent contractor engagement.
• Fully remote with flexible working hours.
• Expected commitment of approximately 20–40 hours per week.
• Project duration may be extended, shortened, or concluded based on project requirements and individual performance.
• Work does not require access to confidential or proprietary information from any current or former employer.
• Payments are issued weekly based on approved work completed.
• At this time, we are unable to support H1-B or STEM OPT candidates.