Remote ASIC & SoC Design and Verification Engineer

Weekday 1; United States; Remote; USD 96,000 - 138,000; Part time

Job summary

Weekday 1 is seeking experienced ASIC/SoC design and verification engineers for a fully remote, part-time engagement to advance next-generation AI hardware understanding. You will contribute RTL development, debugging, and silicon evaluation to improve AI model capabilities.

Ideal candidates have production silicon or tapeout experience and strong SystemVerilog/Verilog skills. The role requires 20–40 hours weekly with remote collaboration and weekly payments.

Qualifications

• Hands-on ASIC/SoC design and/or verification experience.
• Proficient in SystemVerilog and Verilog.
• Experience with production silicon or tapeout projects.
• Knowledge of interface protocols, CDC, handshaking.
• RTL Design and Microarchitecture.
• Functional Verification (UVM, SVA, Cocotb, testbench development).
• IP Integration and SoC Bring-up (AXI, PCIe, DDR, NoC, ARM-based systems).
• Formal Verification and Coverage Closure.
• Timing Closure, Synthesis, Power, Performance, and Area (PPA) Optimization.
• Analog/Mixed-Signal Design Verification.
• Hardware Specification Development and Documentation.

Responsibilities

• Design realistic chip architecture, RTL, debugging, and verification challenges based on real engineering experience.
• Develop complete reference solutions, including RTL implementations, verification environments, testbenches, and documentation using Verilog/SystemVerilog.
• Evaluate AI-generated hardware solutions, identify strengths/weaknesses, provide technical feedback.
• Analyze where AI models struggle with hardware concepts, debugging, verification strategies, and design trade-offs.
• Collaborate with hardware engineers to maintain consistency and high-quality engineering standards.
• Help improve AI understanding of modern digital design methodologies and semiconductor workflows.

Skills

ASIC/SoC design

SystemVerilog/Verilog

EDA tools

System-level HW concepts

RTL Design

Functional Verification

IP Integration & SoC Bring-up

Formal Verification

Timing & PPA optimization

Analog/Mixed-Signal Verification

Technical Documentation

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

VC Formal

Verdi

Icarus Verilog

Verilator

Cocotb

Yosys

OpenROAD

Job description

Weekday 1 is seeking experienced ASIC/SoC design and verification engineers for a fully remote, part-time engagement to advance next-generation AI hardware understanding. You will contribute RTL development, debugging, and silicon evaluation to improve AI model capabilities.

Ideal candidates have production silicon or tapeout experience and strong SystemVerilog/Verilog skills. The role requires 20–40 hours weekly with remote collaboration and weekly payments.