Rad-Hard Digital Design Lead (RTL & Verification)

Renesas Electronics; Palm River (FL); On-site; USD 120,000 - 180,000; Full time

Job summary

Renesas Electronics seeks an experienced Digital Design Engineer for its RadHard product team. The role focuses on designing high-performance, radiation-hardened mixed-signal ICs and supporting mixed-signal verification environments.

The candidate will contribute across specification, design, synthesis, verification, and silicon debug, and will help integrate AMS and DV verification into a unified plan. Strong English communication is required.

Qualifications

• 10+ years' experience in Verilog RTL coding and Verilog family for ASICs and FPGAs.
• MS EE or PhD with strong digital design background.
• Experience with design constraints and synthesis scripts.
• Experience with behavioral top-level modeling and mixed-signal verification methodology.
• Experience with scan insertion and ATPG generation.
• Able to work independently with limited supervision; well organized, self-motivated.
• Fluent in written and spoken English.

Responsibilities

• Involved in spec, design, synthesis, verification, timing, design for test, and silicon debugging.
• Architect RTL for digital interfaces, controllers, state machines, and algorithms.
• Perform synthesis and achieve timing convergence.
• Develop and verify self-tested test benches for mixed-signal devices.
• Strive for maximal verification coverage efficiently.
• Integrate AMS and DV verification plans into a master verification plan.
• Ensure project goals and schedules are met.
• Drive continuous improvement at personal, team, project and company level.

Skills

Verilog RTL

VerilogAMS

VerilogA

SystemVerilog

Education

MSEE/PhD

Tools

Cadence Design Tools

Synopsys DC

Cadence AMS design flow

Job description

Renesas Electronics seeks an experienced Digital Design Engineer for its RadHard product team. The role focuses on designing high-performance, radiation-hardened mixed-signal ICs and supporting mixed-signal verification environments.

The candidate will contribute across specification, design, synthesis, verification, and silicon debug, and will help integrate AMS and DV verification into a unified plan. Strong English communication is required.