Principal Electrical Engineer

Renesas Electronics

Palm River (FL)

On-site

USD 120,000 - 180,000

Full time

3 days ago
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Job summary

Renesas Electronics seeks an experienced Digital Design Engineer for its RadHard product team. The role focuses on designing high-performance, radiation-hardened mixed-signal ICs and supporting mixed-signal verification environments.

The candidate will contribute across specification, design, synthesis, verification, and silicon debug, and will help integrate AMS and DV verification into a unified plan. Strong English communication is required.

Qualifications

  • 10+ years' experience in Verilog RTL coding and Verilog family for ASICs and FPGAs.
  • MS EE or PhD with strong digital design background.
  • Experience with design constraints and synthesis scripts.
  • Experience with behavioral top-level modeling and mixed-signal verification methodology.
  • Experience with scan insertion and ATPG generation.
  • Able to work independently with limited supervision; well organized, self-motivated.
  • Fluent in written and spoken English.

Responsibilities

  • Involved in spec, design, synthesis, verification, timing, design for test, and silicon debugging.
  • Architect RTL for digital interfaces, controllers, state machines, and algorithms.
  • Perform synthesis and achieve timing convergence.
  • Develop and verify self-tested test benches for mixed-signal devices.
  • Strive for maximal verification coverage efficiently.
  • Integrate AMS and DV verification plans into a master verification plan.
  • Ensure project goals and schedules are met.
  • Drive continuous improvement at personal, team, project and company level.

Skills

Verilog RTL
VerilogAMS
VerilogA
SystemVerilog

Education

MSEE/PhD

Tools

Cadence Design Tools
Synopsys DC
Cadence AMS design flow

Job description

Renesas is looking for an experienced Digital Design Engineer for our RadHard product team. This team develops high performance, radiation-hardened mixed-signal integrated solutions.

The environment is fast paced and team members are empowered to make decisions within the scope of their job function. The successful candidate will be responsible for designingdigital circuits and supporting the mixed-signal verification environment.

Renesas is looking for an experienced Digital Design Engineer for our RadHard product team. This team develops high performance, radiation-hardened mixed-signal integrated solutions.

The environment is fast paced and team members are empowered to make decisions within the scope of their job function. The successful candidate will be responsible for designingdigital circuits and supporting the mixed-signal verification environment.

Job Description
  • Actively involved in all stages of product development including specification, design, synthesis, verification, timing analysis, design for test and silicon debug.
  • Architecting and writing the RTL for such circuits as digital interfaces, controllers, state machines and algorithms.
  • Performing synthesis and achieving timing convergence.
  • Develop and verify self-tested test benches for Mixed-signal chips and sub-circuits.
  • Strives for maximal verification coverage in the most time efficient manner.
  • Works with team to integrate the AMS and DV verification plans into one Master verification plan.
  • Works diligently to accomplish project goals and meet schedule requirements.
  • Drives towards continuous personal, team, project and Company improvement
Qualifications
Required
  • 10+ years' experience in Verilog RTL coding and versed in VerilogAMS, VerilogA, Verilog (or SV) languages for both ASICs and FPGAs
  • MSEE/PhD with relevant work experience with a strong background in digital design
  • Proficient developing design constraints and Synthesis scripts.
  • Experience with behavioral top level modeling and mixed signal verification methodology.
  • Experience with scan insertion and ATPG generation.
  • Must be able to work independently with limited supervision. Must be very organized, self-motivated and passionate about the work.
  • Language skills: Written and verbal English language proficiency required.
  • Tools: Cadence Design Tools and Synopsys DC proficiency required. Cadence AMS design flow experience is a definite plus.
Preferred
  • PhD in EE
  • 15+ years' experience Digital design
  • Radiation Harden (Rad-Hard) experience
Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier. With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Are you ready to join our team and shape the future with us?

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.

Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.

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