Rad-Hard Mask Designer: Analog & Mixed-Signal Layout

Renesas Electronics

Palm Bay (FL)

On-site

USD 120,000 - 160,000

Full time

14 days+

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Job summary

Renesas Electronics seeks an experienced mask designer to join the Rad Hard Precision Design Group in either Palm Bay, FL or Research Triangle Park, NC. The role focuses on top-level and cell-level layouts for space market products, utilizing Cadence tool sets and collaborating with circuit, layout, and CAD teams.

The ideal candidate has extensive experience in analog/power/mixed-signal IC layouts, knowledge of layout methodologies, and familiarity with BCD/SOI processes, with strong

Qualifications

  • Minimum fifteen years experience working with analog, power or mixed signal IC layouts.
  • Good working knowledge of IC layout methodologies, flows and CAD tools such as Cadence Virtuoso layout physical verification.

Responsibilities

  • Work at multiple levels of hierarchy from top-level layout floor planning to macro/block level routing.
  • Collaborate with circuit designers to build physical design floorplan and create package bond diagrams.
  • Create high performance analog and mixed signal cell layout and verification.
  • Complete the physical layout design with constraints of circuit design requirements.
  • Verify the layout to meet circuit and process requirements.
  • Execute mask data release and archiving.
  • Use new tools and methods with CAD/CAE to improve layout quality and efficiency.

Skills

Layout design
Analog/mixed-signal
Communication

Tools

Cadence Virtuoso
CAD tools

Job description

Renesas Electronics seeks an experienced mask designer to join the Rad Hard Precision Design Group in either Palm Bay, FL or Research Triangle Park, NC. The role focuses on top-level and cell-level layouts for space market products, utilizing Cadence tool sets and collaborating with circuit, layout, and CAD teams.

The ideal candidate has extensive experience in analog/power/mixed-signal IC layouts, knowledge of layout methodologies, and familiarity with BCD/SOI processes, with strong

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