R&D Engineer IC Design 5

Broadcom; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) participation including company

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Company paid holidays

Paid sick leave

Vacation time

Paid Family Leave

Job summary

Broadcom seeks an experienced ASIC verification engineer to join the system-level verification team. You will develop complex verification environments, create comprehensive test plans, and verify high‑performance network switch ASIC/FPGA designs.

This hands-on role spans from testbench architecture to full verification closure, requiring collaboration with system architects, design and verification teams, and a track record of multiple tape-outs.

Qualifications

• 8+ years ASIC design/verification experience with Verilog
• Bachelor's in Engineering
• Strong knowledge of object-oriented programming and modern ASIC verification flows (UVM/SystemVerilog)
• mastery of Verilog for simulation and familiarity with ASIC design flows for deep sub-micron technologies
• Experience with networking protocols (Ethernet, PCIe, routing/switching) is a major plus
• Must have completed multiple ASIC tape-outs from concept to production
• Excellent technical and business English communication

Responsibilities

• Develop complex verification environments and test plans
• Verify high-performance network switch ASIC/FPGA blocks
• Hands-on implementation across all ASIC verification aspects
• Collaborate with system architects, design engineers, and verification teams
• Architect testbenches from initial concept through full production

Skills

Verilog

C/C++

OOP

UVM

SystemVerilog

Networking knowledge

Communication

Education

Bachelor's in Engineering

Tools

Verilog simulators

Job description

Job Description

This individual will be a key member of the ASIC system-level verification team. Responsibilities include developing complex verification environments, creating comprehensive test plans, and verifying high-performance network switch ASIC/FPGAs. The role involves hands‑on implementation across every aspect of ASIC verification while collaborating closely with system architects, design engineers, and verification teams. The ideal candidate will have a proven track record of completing multiple successful ASIC design and verification cycles—from architecting testbenches (networking background preferred) to achieving full verification closure.

Education & Experience

• Experience: 8+ years of ASIC design/verification experience, including a complete understanding of Verilog design and hands‑on experience with C/C++.


• Education: Bachelor's in Engineering


• Methodologies & Languages: Strong working knowledge of object‑oriented programming (OOP) and modern ASIC verification flows (e.g., UVM/SystemVerilog).


• Technical Depth: Complete mastery of Verilog for simulation and familiarity with ASIC design flows for deep sub‑micron technologies.


• Domain Knowledge: Experience with networking protocols (e.g., Ethernet, PCIe, routing/switching) is a major plus.


• Track Record: Must have completed multiple ASIC tape‑outs, with at least one project taken from initial concept through full production.


• Communication: Fully comfortable with technical and business English across documentation, cross‑functional collaboration, and executive communications.

Compensation And Benefits

The annual base salary range for this position is USD 143,800.00 To USD 230,000.00.

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

• Medical, dental and vision plans


• 401(K) participation including company matching


• Employee Stock Purchase Program (ESPP)


• Employee Assistance Program (EAP)


• Company paid holidays


• Paid sick leave


• Vacation time


• Paid Family Leave

The company follows all applicable laws for Paid Family Leave and other leaves of absence.