Quantum Qubit Design Engineer - Silicon Spin Qubits

Intel; New York (NY); On-site; USD 142,000 - 269,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Vacation

Job summary

Intel is seeking a Quantum Design Engineer to join the Quantum Computing Group in the US. You will contribute to scaling silicon-based quantum processors, from concept to tapeout, collaborating across qubit, control, and software teams to ensure silicon runs in fab and system integration.

Role involves design automation, qubit routing, PDK integration, and signal integrity optimization for large-scale qubit processors.

Qualifications

• Bachelor's degree with 4 years of experience (or master's with 3 years or PhD) in Physics, Electrical Engineering, Cryogenic Engineering, Quantum Technologies, or related field.
• Experience with EM modeling and signal integrity/crosstalk analysis for high-speed interconnects.
• Design automation flow and scripts (e.g., TCL) and knowledge of PDK/process file models.
• Familiarity with industry standard validations (DRC, LVS, Extraction).

Responsibilities

• Collaborate with lithography, process integration, measurement, and PDK teams to establish qubit processes.
• Architect qubit/readout cell design and automation; develop routing for large-scale quantum processors.
• Engage with TCAD/PDK engineers and tool vendors to create process files and models.
• Partner with quantum software/control teams to evaluate error-correction tradeoffs and qubit topology.
• Develop design automation and automated place-and-route flows for qubit routing.

Skills

Excellent communication

Leadership potential

Analytical thinking

Team collaboration

Education

Degree in Physics/Engineering

Tools

EM modeling tools

Design automation tools

APR tooling (TCL)

PDK workflows

Job description

Intel is seeking a Quantum Design Engineer to join the Quantum Computing Group in the US. You will contribute to scaling silicon-based quantum processors, from concept to tapeout, collaborating across qubit, control, and software teams to ensure silicon runs in fab and system integration.

Role involves design automation, qubit routing, PDK integration, and signal integrity optimization for large-scale qubit processors.