Quantum Chip Design Enablement Engineer

Entangled Future; College Park (MD); Hybrid; USD 120,000 - 160,000; Full time

Job summary

IonQ in College Park, MD is seeking a Quantum Design Enablement Engineer to join our Manufacturing team. You will act as the primary tech interface between internal quantum chip designers and external foundry partners, ensuring transistor-like designs transition to reliable fabrication.

In this mid-level, full-time role you will manage the tapeout flow, perform physical verification, and collaborate on refining the Process Design Kit (PDK).

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Physics, Materials Science, or related field.
• 3–5 years in semiconductor manufacturing, design enablement, or tapeout operations.
• Hands-on with physical verification tools (Calibre, Pegasus, IC Validator) and DRC/LVS/ERC checks.
• Proficiency with layout/viewing tools (Cadence Virtuoso, KLayout) and layout edits.
• Strong understanding of PDK architecture and foundry design rules.
• Excellent cross-functional communication to align with fab engineers and design teams.
• Proficient in Python and Python-based layout generation (gdsfactory, gdspy, KLayout); Git.

Responsibilities

• Serve as primary technical interface with external foundry partners.
• Define, implement, and refine tapeout flow and PDK management.
• Perform hands-on layout for test structures and reticle assembly.
• Collaborate with foundries to align process design kits to fabrication needs.

Skills

Semiconductor design enablement

Tapeout operations

Physical verification

Layout editing

PDK management

Python programming

Git version control

Education

Bachelor’s or Master’s degree in Electrical Engineering, Physics, Materials Science, or related field

Tools

Siemens Calibre

Cadence Pegasus

Synopsys IC Validator

Cadence Virtuoso

KLayout

Job description

IonQ in College Park, MD is seeking a Quantum Design Enablement Engineer to join our Manufacturing team. You will act as the primary tech interface between internal quantum chip designers and external foundry partners, ensuring transistor-like designs transition to reliable fabrication.

In this mid-level, full-time role you will manage the tapeout flow, perform physical verification, and collaborate on refining the Process Design Kit (PDK).