Quantum Qubit Design Engineer for Scalable Silicon Chips

Intel; Phoenix (AZ); On-site; USD 142,000 - 269,000; Full time

Job summary

Intel's Quantum Computing Group in the US is seeking an exceptional Quantum Design Engineer to scale qubit processors from concept to tapeout. You will work with qubit, control, system integration and software teams across the Intel ecosystem to push the boundaries of quantum technology.

The role emphasizes leading edge design, process integration, and hardware-software collaboration, with a focus on silicon spin qubits, PDK development, and large-scale routing for quantum processors.

Qualifications

• Bachelor's degree with 4+ years of experience or advanced degree in Physics, Electrical Engineering, Cryogenic Engineering, Quantum Technologies or related field.
• Experience with EM modeling and simulation for high-speed interconnects.
• Design automation flow implementation and universal process file models and extraction.

Responsibilities

• Establish qubit processes and design rules with lithography, process integration, measurement and PDK engineers.
• Architect qubit and readout element standard cell design and automation.
• Collaborate with TCAD/PDK engineers and tool vendors to create qubit process files and models.
• Analyze tradeoffs on quantum error correction schemes vs qubit topology.
• Develop automated place-and-route flows for qubit routing and large-scale processors.
• Work with external customers to understand needs and provide Intel quantum PDK solutions.

Skills

EM modeling

Signal integrity

Design automation

Scripting (TCL)

Education

Bachelor's or higher in Physics / Electrical Engineering / Quantum Tech

Tools

SKILL

VSR

MSOA

Job description

Intel's Quantum Computing Group in the US is seeking an exceptional Quantum Design Engineer to scale qubit processors from concept to tapeout. You will work with qubit, control, system integration and software teams across the Intel ecosystem to push the boundaries of quantum technology.

The role emphasizes leading edge design, process integration, and hardware-software collaboration, with a focus on silicon spin qubits, PDK development, and large-scale routing for quantum processors.