Senior Quantum Processor Design Engineer

NightDragon Acquisition Corp.

College Park (MD)

On-site

USD 124,000 - 186,000

Full time

5 days ago
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Benefits offered by this job

Medical/Dental/Vision
401(k) matching
Unlimited PTO
Paid holidays
Parental leave
Legal insurance
Home tech stipend

Job summary

IonQ, Inc. is seeking a Senior QPU Design Engineer to join the Processor Design team at Oxford Ionics, now part of IonQ. You will translate requirements into chip layout and work with scientists and fabrication engineers to bring ion-trap chip designs into production.

You’ll guide multi-layer chip layouts, collaborate across teams to ensure feasibility, and take ownership of final tape-out, with experience in GDSFactory Python, Cadence, and ion trap/photonics design areas valued.

Qualifications

  • Hands-on experience translating design requirements into features for complex chips.
  • Experience laying out multi-layer chips, metal-track routing, and interfaces with photonics/CMOS.
  • Ability to work across teams to discuss requirements, agree specifications and ensure feasibility.

Responsibilities

  • Guiding chips through the design process from requirements to layout and tape-out.
  • Laying out complex multi-layer chips with metal-track routing and photonics/CMOS interfaces.
  • Collaborating with scientists to discuss requirements and settle specifications.
  • Coordinating with other teams to ensure feasibility and compatibility.
  • Taking charge of projects independently and delivering final tape-out.

Skills

chip layout
GDSFactory in Python
ion trap design
photonics design

Tools

Cadence for IC layout
GDSFactory

Job description

IonQ, Inc. is seeking a Senior QPU Design Engineer to join the Processor Design team at Oxford Ionics, now part of IonQ. You will translate requirements into chip layout and work with scientists and fabrication engineers to bring ion-trap chip designs into production.

You’ll guide multi-layer chip layouts, collaborate across teams to ensure feasibility, and take ownership of final tape-out, with experience in GDSFactory Python, Cadence, and ion trap/photonics design areas valued.

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