Project Design Lead: ML-Enhanced Digital ICs

nexperia; San Jose (CA); Hybrid; USD 160,000 - 220,000; Full time

Benefits offered by this job

Telecommuting up to 3 days per week

Job summary

Nexperia USA Inc. in San Jose, CA seeks a Project Design Lead to architect and verify digital logic in mixed-signal ICs. You will analyze RTL code, perform static checks like Lint, CDC, and RDC, and collaborate with firmware and CAD teams for pre-silicon validation.

The role involves ML-driven verification improvements, FPGA prototyping, and post-silicon analysis to ensure silicon matches models. Telecommuting up to 3 days weekly is supported.

Qualifications

• Minimum 2 years of digital IC design and verification experience.
• Experience with RTL design using Verilog or SystemVerilog.
• Experience with static design checks (Lint, CDC, RDC).
• Experience with FPGA prototyping and pre-silicon validation.
• Experience in post-silicon debugging and using AI/ML tools in design automation.

Responsibilities

• Design digital logic blocks for mix-signal ICs according to specs.
• Perform static checks, CDC analysis, and RDC validation.
• Analyze simulation, synthesis, and timing across PVT conditions.
• Develop ML/AI-based tools to optimize verification workflows.
• Collaborate with analog, software, and CAD teams for pre-silicon validation.

Skills

Digital IC design

Verification

RTL design (Verilog/SystemVerilog)

AI/ML in design automation

Debugging and post-silicon analysis

Simulation/diagnostic tools

FPGA prototyping

Lint, CDC, RDC experience

Team collaboration across disciplines

Education

Master’s degree in Electrical Engineering, Computer Engineering, or related field

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 4 years experience

Tools

Cadence Xcelium

Job description

Nexperia USA Inc. in San Jose, CA seeks a Project Design Lead to architect and verify digital logic in mixed-signal ICs. You will analyze RTL code, perform static checks like Lint, CDC, and RDC, and collaborate with firmware and CAD teams for pre-silicon validation.

The role involves ML-driven verification improvements, FPGA prototyping, and post-silicon analysis to ensure silicon matches models. Telecommuting up to 3 days weekly is supported.