Project Design Lead (EX)

nexperia; San Jose (CA); Hybrid; USD 160,000 - 220,000; Full time

Benefits offered by this job

Telecommuting up to 3 days per week

Job summary

Nexperia USA Inc. in San Jose, CA seeks a Project Design Lead to architect and verify digital logic in mixed-signal ICs. You will analyze RTL code, perform static checks like Lint, CDC, and RDC, and collaborate with firmware and CAD teams for pre-silicon validation.

The role involves ML-driven verification improvements, FPGA prototyping, and post-silicon analysis to ensure silicon matches models. Telecommuting up to 3 days weekly is supported.

Qualifications

• Minimum 2 years of digital IC design and verification experience.
• Experience with RTL design using Verilog or SystemVerilog.
• Experience with static design checks (Lint, CDC, RDC).
• Experience with FPGA prototyping and pre-silicon validation.
• Experience in post-silicon debugging and using AI/ML tools in design automation.

Responsibilities

• Design digital logic blocks for mix-signal ICs according to specs.
• Perform static checks, CDC analysis, and RDC validation.
• Analyze simulation, synthesis, and timing across PVT conditions.
• Develop ML/AI-based tools to optimize verification workflows.
• Collaborate with analog, software, and CAD teams for pre-silicon validation.

Skills

Digital IC design

Verification

RTL design (Verilog/SystemVerilog)

AI/ML in design automation

Debugging and post-silicon analysis

Simulation/diagnostic tools

FPGA prototyping

Lint, CDC, RDC experience

Team collaboration across disciplines

Education

Master’s degree in Electrical Engineering, Computer Engineering, or related field

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 4 years experience

Tools

Cadence Xcelium

Job description

Project Design Lead, Nexperia USA Inc., San Jose, CA:

Design digital logic circuits for integration into mixed-signal integrated circuits (ICs), including finite state machines, control logic, data path components, and interface blocks, based on product requirements and system architecture specifications. Perform static design verification including Lint checking to ensure code quality, Clock Domain Crossing (CDC) analysis to validate synchronization of asynchronous clocks and Reset Domain Crossing (RDC) analysis to confirm correct handling of resets across domains. Analyze simulation, synthesis, and timing reports to validate design quality and correct operation under different process-voltage-temperature (PVT) conditions. Conduct applied research into machine learning (ML) or artificial intelligence (AI) techniques for the purpose of improving digital design and verification flows, including automation of test generation, design space exploration, and bug triage. Translate system and product definition documents into digital architecture, block-level specifications, and micro-architecture definitions, and document digital design implementation details. Generate behavioral models of analog or mixed-signal components using high-level modeling techniques (e.g., SystemVerilog, Verilog-A) to enable mixed-signal simulation and validate digital-analog interaction early in the design process. Build Field Programmable Gate Array (FPGA) prototypes for digital logic emulation, perform functional tests using application-level scenarios, and collaborate with firmware teams for pre-silicon validation and debugging. Participate in post-silicon bring-up by analyzing lab measurements and test data, identifying root causes of issues, comparing silicon behavior with simulation models, and recommending fixes or design changes. Develop scripts, ML models, or AI-based tools to optimize verification workflows, automate debugging tasks, extract features from simulation datasets, and enhance RTL code quality and coverage metrics. Collaborate with cross-functional teams including analog designers, system engineers, software developers, and CAD/methodology engineers to define requirements and integrate AI-enhanced solutions into production design workflows.

Full time employment, Monday – Friday, 40 hours per week, $188,760.00 per year.

MINIMUM REQUIREMENTS:

Must have a Master’s degree in Electrical Engineering, Computer Engineering, or a related field and 2 years of experience in digital integrated circuit (IC) design and verification.

Alternatively, the employer will accept a Bachelors degree in Electrical Engineering, Computer Engineering, or a related field and 4 years of experience in digital integrated circuit (IC) design and verification.

Must have 2 years of experience in each of the following:

• Experience with digital circuit design and verification for mix-signal chip products;
• Experience using simulation tools, including Cadence Xcelium, to debug design issues in RTL and analyze RTL code coverage;
• Experience working in at least one project in verification environment and platform setup;
• Experience working in at least one project in digital function design;
• Experience with RTL design using Verilog or SystemVerilog;
• Experience with static design checks including Lint, CDC, and RDC;
• Experience with FPGA prototyping and pre-silicon validation;
• Experience with post-silicon debugging; and
• Experience using AI/ML tools in digital design automation.

Telecommuting permitted up to 3 days per week.

Nexperia is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, color, creed, religion, national origin, ancestry, citizenship status, age, sex or gender (including pregnancy, childbirth and pregnancy-related conditions), gender identity or expression (including transgender status), sexual orientation, marital status, military service and veteran status, physical or mental disability, genetic information, or any other characteristic protected by applicable federal, state or local laws and ordinances. Nexperia’s management team is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, TeamNexperian’s activities, access to facilities and programs and general treatment during employment.

D&I Statement

As an equal-opportunity employer, Nexperia values diversity not just because it is the right thing to do but because diverse teams perform better. We are dedicated to being inclusive, and a proof point of this dedication is that we were the main partner of the very first Dutch Paralympic Team NL House during the Paris 2024 Paralympic Games. Our recruitment process is inclusive and accessible to all, and we consider all applicants fairly, as well as providing a safe work environment and reasonable adjustments where requested.

In addition, we offer our colleagues the possibility to join employee resource groups such as the Pride Network Group or global and local Women's groups. Nexperia is committed to increasing women in management positions to 30% by 2030.