Principal Verification Engineer

OSI Engineering; San Jose (CA); Hybrid; USD 170,000 - 196,000; Full time

Job summary

A leading chip provider in California seeks a Principal Verification Engineer to lead verification strategies across product lines. Ideal candidates will have expertise in System Verilog and UVM methodology, with responsibilities including mentoring junior engineers and developing verification flows. This full-time hybrid role offers a salary range of $170,000–$196,000 based on experience.

Qualifications

• 10+ years of verification experience or 7+ years with a PhD.
• Experience with DDR memory interfaces is desirable.
• Demonstrated ability to lead complex technical solutions.

Responsibilities

• Define verification plans with team architects.
• Implement testbenches using UVM methodology.
• Mentor and guide junior engineers.

Skills

System Verilog expertise

UVM methodology experience

Collaboration across teams

Education

MS in Electrical Engineering

PhD in EE

Tools

Synopsys VCS

Cadence Xcelium

Jenkins

Job description

Overview

A leading chip and silicon IP provider is seeking a talented Principal Verification Engineer to join its Memory Interconnect Design team. In this full-time hybrid role, you’ll work alongside world-class engineers to develop advanced technologies that make data faster and more secure. As a key technical leader in the organization, the Principal Verification Engineer will be responsible for defining and executing verification strategies across multiple product lines and global sites. The ideal candidate will bring deep technical expertise, ownership mentality, and strong collaboration skills to help ensure robust, production-ready silicon.

Responsibilities

• Technical leader for full-chip and block-level verification
• Define verification plans in coordination with Architects, Logic, and Mixed-Signal Designers
• Implement testbenches, monitors, and scoreboards using UVM methodology
• Achieve functional and code coverage goals to ensure quality and completeness
• Support silicon bring-up, lab testing, and debug in partnership with the System team
• Contribute to the development of verification flows, tools, and methodology
• Mentor and guide junior engineers within the team

Requirements

• Proficient in System Verilog or Verilog with significant UVM methodology experience
• Significant Experience with standard ASIC Verification flow/software tools
• Simulation tools: Synopsys VCS, Cadence Xcelium
• Coverage & Analysis: Cadence IMC (Incisive Metrics Center)
• Experience with scripting in Linux/Unix environments
• Verification of DDR memory interfaces is desirable
• Experience working in Analog/Mixed-Signal Products is desirable
• Verification Methodologies: SVA (System/Verilog Assertions) is desirable
• Regression Management: Jenkins (CI/CD Integration) is desirable
• Demonstrated ability to lead and drive complex technical solutions
• A strong commitment & ability to work in cross functional and globally dispersed teams
• MS in Electrical Engineering and 10+ years, or PhD in EE and 7+ years of verification experience

Location: San Jose, CA; Agoura Hills, CA; Morrisville, NC; Johns Creek, GA (Hybrid)

Type: Full-time

Salary Range: $170,000–$196,000 (DOE)

No 3rd party agencies or C2C

Seniority level

• Mid-Senior level

Employment type

• Contract

Industries

• Appliances, Electrical, and Electronics Manufacturing

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