Design Verification Engineer

Infotree Global Solutions; Santa Clara (CA); On-site; USD 130,000 - 213,000; Full time

Job summary

A leading technology company in Santa Clara is seeking a Design Verification Engineer who will work on improving the quality of designs and collaborate with cross-functional teams. The ideal candidate will have extensive experience in ASIC design verification, strong skills in C/C++, and a background in computer engineering. Offering a competitive pay ranging from $80/hr to $90/hr.

Qualifications

• 10+ years of ASIC design verification experience.
• Proficient in debugging firmware and RTL code using simulation tools.
• Experience/Background with DDR or Memory Controller is a plus.

Responsibilities

• Develop/Maintain tests for functional verification.
• Build directed and random verification tests, debug test failures.
• Work on functional & code coverage verification.

Skills

C/C++

Verilog

System Verilog

Python

Perl

TCL

Education

Bachelor’s or master’s degree in computer engineering/Electrical Engineering

Job description

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Infotree Global Solutions provided pay range

This range is provided by Infotree Global Solutions. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$80.00/hr - $90.00/hr

Direct message the job poster from Infotree Global Solutions

We are looking for an adaptive, self-motivative Design Verification Engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve client's abilities to deliver the highest quality, industry-leading technologies to market. Be a part of a team that delivers Industry leading IP and help our experts in RTL, FW, circuit, and architecture teams develop leading edge and differentiating IPs.

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Develop/Maintain tests for functional verification.

• Build the directed and random verification tests, debug test failures to determine the root cause, work with RTL and firmware engineers to resolve design defects and correct any test issues.

• Work on functional & code coverage verification.

• Provide technical support to other teams

PREFERRED EXPERIENCE:

• Experience with C/C++

• Experience with Verilog, System Verilog, and modern verification libraries like UVM

• 10+years of ASIC design verification experience

• Experience / Background with DDR or Memory Controller. PHY Verification is a plus

• Experience with scripting languages like Python, Perl and TCL is a plus.

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified

• Understanding of Design for Test methodologies and DFT verification experience is a plus

• Proficient in debugging firmware and RTL code using simulation tools

ACADEMIC CREDENTIALS:

• Bachelor’s or master’s degree in computer engineering/Electrical Engineering

Seniority level

• Seniority level

  Not Applicable

Employment type

• Employment type

  Contract

Job function

• Industries

  Semiconductor Manufacturing

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