Principal SOC Design Engineer – Clocking & Verification

Cadence Design Systems; San Jose, Northern (CA, KY); Hybrid; USD 140,000 - 260,000; Full time

Job summary

Cadence Design Systems in San Jose is seeking a Principal Design Engineer to lead SOC/sub-system projects, drive timing closure, and oversee physical verification for tape-out readiness. You will collaborate with Front End RTL and Back End teams to optimize RTL synthesis, floor planning, clock trees, and power integrity.

The ideal candidate has Cadence tool expertise (Innovus, Tempus, QRC, Voltus, Pegasus), strong leadership, and hands-on experience with advanced nodes and PCIe/DDR interfaces.

Qualifications

• BS in Electrical Engineering with 7+ years, MS with 5+ years, or PhD with 1+ year.
• Experience with Cadence tools: Innovus, Tempus, QRC, Voltus, Pegasus.
• Synthesis, floor planning, clock trees, timing closure.
• Knowledge of PCIe, DDR, LPDDR, SRAM, UCIe interfaces.
• Lead teams for SOCs or sub-systems.

Responsibilities

• Lead a team to implement SOCs or sub-system chips.
• Work on RTL synthesis and floor planning.
• Build clock trees and perform optimizations.
• Close timing, IR drop and physical verification.
• Review and document designs for taping out.

Skills

Team leadership

Scripting (Shell/Perl/TCL)

Problem solving

Education

BS in Electrical Engineering

MS in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Innovus

Cadence Tempus

Cadence QRC

Cadence Voltus

Cadence Pegasus

Job description

Cadence Design Systems in San Jose is seeking a Principal Design Engineer to lead SOC/sub-system projects, drive timing closure, and oversee physical verification for tape-out readiness. You will collaborate with Front End RTL and Back End teams to optimize RTL synthesis, floor planning, clock trees, and power integrity.

The ideal candidate has Cadence tool expertise (Innovus, Tempus, QRC, Voltus, Pegasus), strong leadership, and hands-on experience with advanced nodes and PCIe/DDR interfaces.