Principal SerDes Architect for High-Speed AI Interconnects

Celero Communications, Inc.; United States; Remote; USD 190,000 - 260,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal SerDes Design Engineer to lead the architecture, specifications, and circuit topologies for next-generation SerDes in AI interconnect transceivers.

You will drive system-level modelling, including MATLAB, SystemVerilog, and Verilog-A, to analyze link budgets, jitter budgeting, and equalization strategies. You will design high-performance analog/mixed-signal blocks and oversee layout, lab validation, and silicon-verification activities.

Qualifications

• Requires master’s degree or PhD in Electrical Engineering or related field with 10+ years of SerDes design experience.
• Experience taking high-speed SerDes designs to tape-out and volume production.
• Strong lab bring-up, characterization, and debugging skills for production-ready IP.

Responsibilities

• Define architecture, specifications, and topologies for next-generation SerDes.
• Develop system-level models (MATLAB, SystemVerilog, Verilog-A) for link budgets and jitter budgeting.
• Design high-performance analog/mixed-signal circuits in advanced nodes (16/12nm and below).
• Develop critical blocks (CTLE, DFE, PLLs, DLLs, TDCs) and calibrations.
• Oversee physical layout to minimize parasitics and variation impacts.
• Lead lab validation and correlate silicon measurements with simulations.

Skills

SerDes design

Tape-out & volume production

Lab bring-up & debugging

Advanced node technologies

Cross-functional collaboration

Documentation & communication

Education

Master’s degree or PhD in Electrical Engineering

Tools

MATLAB

SystemVerilog

Verilog-A

Job description

Celero Communications, Inc. is seeking a Principal SerDes Design Engineer to lead the architecture, specifications, and circuit topologies for next-generation SerDes in AI interconnect transceivers.

You will drive system-level modelling, including MATLAB, SystemVerilog, and Verilog-A, to analyze link budgets, jitter budgeting, and equalization strategies. You will design high-performance analog/mixed-signal blocks and oversee layout, lab validation, and silicon-verification activities.