Principal SerDes Design Engineer

Celero Communications, Inc.; United States; Remote; USD 190,000 - 260,000; Full time

Job summary

Celero Communications, Inc. is seeking a Principal SerDes Design Engineer to lead the architecture, specifications, and circuit topologies for next-generation SerDes in AI interconnect transceivers.

You will drive system-level modelling, including MATLAB, SystemVerilog, and Verilog-A, to analyze link budgets, jitter budgeting, and equalization strategies. You will design high-performance analog/mixed-signal blocks and oversee layout, lab validation, and silicon-verification activities.

Qualifications

• Requires master’s degree or PhD in Electrical Engineering or related field with 10+ years of SerDes design experience.
• Experience taking high-speed SerDes designs to tape-out and volume production.
• Strong lab bring-up, characterization, and debugging skills for production-ready IP.

Responsibilities

• Define architecture, specifications, and topologies for next-generation SerDes.
• Develop system-level models (MATLAB, SystemVerilog, Verilog-A) for link budgets and jitter budgeting.
• Design high-performance analog/mixed-signal circuits in advanced nodes (16/12nm and below).
• Develop critical blocks (CTLE, DFE, PLLs, DLLs, TDCs) and calibrations.
• Oversee physical layout to minimize parasitics and variation impacts.
• Lead lab validation and correlate silicon measurements with simulations.

Skills

SerDes design

Tape-out & volume production

Lab bring-up & debugging

Advanced node technologies

Cross-functional collaboration

Documentation & communication

Education

Master’s degree or PhD in Electrical Engineering

Tools

MATLAB

SystemVerilog

Verilog-A

Job description

Principal SerDes Design Engineer

We are looking for a SerDes Lead Designer, who is seeking an amazing opportunity delivering disruptive High Speed Interconnect Technology to power next generation AI. Candidate will have the opportunity to architect and design SerDes for next generation transceivers.

What You Will Do

• Define architecture, specifications, and circuit topologies for next-generation SerDes
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies and jitter budgeting
• Design high-performance analog/mixed-signal circuits in advanced node technologies
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area
• Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
• Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets
• Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the‑art lab
• Correlate silicon measurements with simulated data, and lead performance optimization in the system environment

What You Will Bring

• Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
• Proven record of taking high-speed SerDes design to tape-out and volume production
• Experience in lab bring-up, characterization, and debugging designs that reach out production
• Must have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs
• Strong communication and documentation skills