Principal Product Engineer - Low Power Emulation

Cadence; Shanghai (VA); On-site; USD 120,000 - 160,000; Full time

Job summary

Cadence is hiring to drive low-power design and verification across multi-voltage domains, supporting customer projects in functional verification and power validation. You will analyze power intent, RTL design, and system integration while collaborating with global R&D teams to deliver robust solutions.

Strong problem-solving and English communication are essential. The role emphasizes customer-facing support and participation in methodology development and best-practice standardization to

Qualifications

• Bachelor’s degree or above in Microelectronics, Electrical Engineering, or related fields.
• Experience in low-power design/verification and/or RTL design/verification.
• Strong English communication skills and ability to work in a global environment.

Responsibilities

• Drive low-power design and verification activities, including UPF modeling and multi-voltage domain design.
• Support customer projects on functional verification and power validation.
• Analyze and debug issues related to power intent, RTL design, and system integration.
• Collaborate with global R&D teams to deliver and optimize technical solutions.
• Provide high-quality technical support and troubleshooting to customers.
• Contribute to methodology development and best-practice standardization.

Skills

Low-power design

RTL design

SystemVerilog/UVM

Power management

Problem solving

English communication

Education

Bachelor's degree in Microelectronics or Electrical Engineering

Tools

Palladium/Protium hardware emulation

EDA tools

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities

• Drive low-power design and verification activities, including UPF modeling, multi-voltage domain design, and power-aware simulation/emulation
• Support customer projects on both functional verification and power validation
• Analyze and debug complex issues related to power intent, RTL design, and system integration
• Collaborate closely with global R&D teams to deliver and optimize technical solutions
• Guide customers to success by providing high-quality technical support and troubleshooting solutions
• Contribute to methodology development, knowledge sharing, and best-practice standardization

Requirements

• Bachelor’s degree or above in Microelectronics, Electrical Engineering, or related fields
• Experience in at least one of the following areas:
  • Low-power design or verification (UPF/CPF/Power-aware verification)
  • RTL design or verification (SystemVerilog/UVM preferred)
• Solid understanding of:
  • SoC architecture and digital design principles
  • Power management techniques (Power domains, Isolation, Retention, DVFS, etc.)
• Strong problem-solving and debugging skills in complex systems
• Good communication skills in English (both verbal and written), able to work in a global environment

Preferred Qualifications

• Experience with Palladium/Protium/hardware emulation platforms
• Familiarity with EDA tools and verification flows
• Customer-facing experience (AE/PE/Solution Engineer)
• Tape-out experience in SoC or ASIC projects
• Experience in power analysis and optimization

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