Sr. Principal Product Engineer

Cadence Design Systems; San Jose (CA); On-site; USD 161,000 - 299,000; Full time

Benefits offered by this job

Paid vacation

401(k) match

Employee stock purchase plan

Medical/Dental/Vision plans

Job summary

Cadence Design Systems seeks a Senior Principal Product Engineer on the Voltus power integrity and reliability platform. You will bridge R&D, applications, and customers, turning complex IR/EM and PDN signoff requirements into scalable product flows.

You will mentor engineers, influence product roadmap with foundry feedback, and champion robust, scalable solutions across advanced-node multiplexing and 3DIC contexts. This role demands leadership and hands-on depth.

Qualifications

• Bachelor's or higher in a relevant engineering field with 6+ years experience for PhD, 8+ for MS, or 10+ for BS.
• Deep hands-on IR/EM (EMIR) and PDN analysis; signoff flows for digital back-end.
• Strong CMOS/digital design background and power integrity signoff expertise.
• Proven ability to diagnose critical issues and drive R&D fixes to deployment.
• Scripting in Tcl and Python; excellent communication with customers and execs.
• Preferred: direct Voltus and Cadence tool experience.

Responsibilities

• Serve as the primary technical interface to R&D for Voltus and drive product requirements.
• Lead enablement for advanced-node IR/EM signoff and PDk readiness and deployment.
• Own complex customer issues across IR/EM, low-power, multi-voltage domains and signoff.
• Define foundry-aligned power and EM modeling assumptions; collaborate with PDK/Extraction.
• Influence roadmap with foundry and customer gaps; mentor engineers and set standards.

Skills

Tcl scripting

Python scripting

Signoff/debug experience

Power integrity

CMOS/digital design

Low-power / multi-power-domain

Issue debugging at scale

Customer/EOP presentations

Education

Bachelor's in Electrical / Electronics / VLSI Engineering

MS in Electrical / Electronics / VLSI Engineering

PhD in Electrical / Electronics / VLSI Engineering

Tools

Voltus

Integrity

Tempus

Innovus

Quantus/QRC

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This Senior Principal Product Engineer is a technical leader on the Voltus product engineering team, working on Cadence's power noise and reliability analysis platform. The role sits between strategic customers/foundries, Applications, and R&D, and is accountable for turning the hardest IR/EM, PDN, and electrothermal signoff requirements into product and flow solutions.

Key Responsibilities

Serve as the primary technical interface to R&D for Voltus, driving product requirements, priorities, and methodology for strategic foundry and customer programs. Lead Voltus enablement for advanced-node IR/EM signoff: flow/techfile/PDK readiness, reference flows, qualification, benchmarking, and production deployment. Own resolution of complex customer issues spanning static/dynamic IR, EM, low-power / multi-voltage domains, hierarchical and full-chip signoff, and related timing/stack-die interactions. Define and validate foundry-aligned power integrity and EM modeling assumptions; partner with PDK, extraction, and signoff teams on advanced-node and 3DIC readiness. Influence product roadmap (including AI-driven IR mitigation, 3DIC, and electrothermal co-analysis) based on foundry and customer gaps. Mentor Lead/Principal PEs and AEs; set debug standards, deployment practices, and issue-tracking discipline for the account/foundry program. Work effectively with customers, Cadence field, Marketing, and R&D across geographies; present findings and recommendations to customer and internal leadership.

Minimum Qualifications

Bachelor's in Electrical / Electronics / VLSI Engineering with 10+ years of related experience, or MS with 8+ years, or PhD with 6+ years. Deep hands-on experience with industry-standard IR/EM (EMIR) and PDN analysis tools and digital physical implementation / signoff flows. Strong background in CMOS/digital design, power IR-drop analysis, circuit analysis, and low-power / multi-power-domain chip power-integrity signoff. Proven ability to separate critical issues from noise, debug large SoC/PDN problems, and close the loop from customer requirement to R&D fix to deployment. Scripting in Tcl and Python; strong written, verbal, and presentation skills with customer and executive audiences. Preferred Direct experience with Voltus and adjacent Cadence digital signoff/implementation tools (Integrity, Tempus, Innovus, Quantus/QRC). 3DIC / chiplet, electrothermal, and advanced FinFET or GAA node experience. Prior technical leadership of PE/AE teams or of a strategic account/foundry program.

Salary and Incentives

The annual salary range for California is $161,000 to $299,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.

Benefits

• paid vacation and paid holidays
• 401(k) plan with employer match
• employee stock purchase plan
• a variety of medical, dental and vision plan options

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences. Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence. Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.