Principal Product Engineer

Cadence Design Systems; San Jose (CA); Hybrid; USD 140,000 - 260,000; Full time

Job summary

Cadence Design Systems in San Jose is seeking a Principal Product Engineer for the Digital and Signoff Group (DSG). You will provide deep place-and-route expertise across RTL to GDSII, work with R&D and customers to optimize timing, PPA, and design flows at 16nm and below.

The role requires an MS in EE with 5+ years in Digital Implementation, strong VLSI timing analysis, and hands-on experience with Synthesis, Physical Design and Signoff tools.

Qualifications

• MS in Electrical Engineering or equivalent.
• 5+ years in Digital Implementation or product engineering.
• Strong understanding of VLSI physical design and timing analysis.

Responsibilities

• Support Cadence products in the Digital and Signoff team.
• Track and debug customer issues with R&D and release teams.
• Run design benchmarks and develop flows and solutions.

Skills

Digital Implementation

VLSI timing analysis

Problem solving

Communication skills

Education

MS in EE

Tools

EDA tools (Synthesis)

Signoff tools

Perl

Tcl

Shell scripting

Job description

## Principal Product EngineerApply: SAN JOSE: Full time: Posted Yesterday: R56481## **At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.**This opportunity is for a Product Engineer in the Digital and Signoff Group (DSG) at Cadence. The Cadence Digital and Signoff Group will offer you a dynamic environment in which you will work with innovative R&D and Customer Engagement teams to influence the development of software tools for advanced chip design platforms. As Product Engineer, you will be a source of technical place and route expertise to Cadence customers and to R&D.You are a motivated and energetic engineer with a deep understanding of ASIC design methodologies and of every stage of the RTL to GDSII flow.You have proven hands-on experience with timing closure and PPA optimization at 16nm and below nodes.You combine your deep understanding with strong analysis skills to debug customer problems and propose solutions, with an organized and coherent approach. You are an excellent communicator.Position Responsibilities:Support Cadence products in the Digital and Signoff team.Track and debug customer issues and work with R&D and release team on issue resolution.Run design benchmarks and develop flows and solutions.Position Requirements:MS in EE with 5+ years of experience in Digital Implementation, either as a design engineer or as a product engineerStrong understanding of VLSI physical design and timing analysis; familiarity with digital implementation challenges including clock tree synthesis, routing optimization and silicon signoff.Experience with industry standard EDA tools in Synthesis, Physical design and Signoff at 16nm and below nodes.Exposure to, and solid understanding of, hierarchical design methodologies and low power designEnergetic team player with a passion for problem solvingStrong analysis skills with a track record to prove itStrong communication skills (verbal and written)Automation skills using Perl, Tcl and shell scripting*The annual salary range for California is $140,000 to $260,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.*