Principal NoC IP Micro-Architect - RTL & SoC Interconnect Lead

altera; San Jose (CA); On-site; USD 209,500 - 299,200; Full time

Job summary

Altera is seeking a Principal NoC IP Micro‑Architect in San Jose, CA to lead end‑to‑end architecture and RTL design for high‑performance interconnect IPs within next‑generation FPGA platforms. You will collaborate across architecture, design, verification, software, physical design, and product teams to optimize power, performance, area, and reliability.

This senior role requires deep expertise in SoC interconnects, NoC fabrics, performance modeling, and system-level optimization, with a track

Qualifications

• 15+ years of related working experience.
• 10+ years of experience in SystemVerilog, VCS/Synopsys simulators, Lint and synthesis.
• 10+ years of experience in programming with C/C++/Perl/Python/TCL/Unix Shell script.
• 10+ years of experience in FPGA design and programming is a plus.
• 10+ years of experience in RTL validation is a plus.
• 10+ years of experience in development of Network on Chip IPs.
• 5+ years of experience using AI to improve development efficiency is a great plus.

Responsibilities

• Develop logic design, RTL coding, and simulation for Network on Chip IPs and potentially other FPGA IPs & subsystem for integration in full chip designs.
• Participate in the definition of architecture and microarchitecture features of the block being designed.
• Create prototypes, simulate models, and specify system requirements.
• Prepare and design logic diagrams and codes for implementing system design and test specifications.
• Deliver software models for device level bring up, including user visible functionality, timing, and power.
• Apply RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with the physical implementation team.
• Utilize advanced EDA tools such as timing constraints, verification, RTL lint, CDC, RDC & DFT to ensure high quality IP development and deploy automation & AI to enhance development efficiency.
• Review the verification plan and implementation to ensure design features are verified correctly and resolve and implement corrective measures for failing RTL tests to ensure correctness of features.
• As a senior designer, groom next‑level technical members, technically oversee & guide the entire NOC team, and proactively anticipate potential design challenges & roadblocks to take mitigation actions, ensuring successful execution of the SS that meets project requirements and schedule.

Skills

RTL design

NoC IP development

SystemVerilog

verification & lint

C/C++/Python

AI for development

FPGA design

Tools

VCS/Synopsys simulators

Lint

Synthesis

Job description

Altera is seeking a Principal NoC IP Micro‑Architect in San Jose, CA to lead end‑to‑end architecture and RTL design for high‑performance interconnect IPs within next‑generation FPGA platforms. You will collaborate across architecture, design, verification, software, physical design, and product teams to optimize power, performance, area, and reliability.

This senior role requires deep expertise in SoC interconnects, NoC fabrics, performance modeling, and system-level optimization, with a track