Principal High-Speed Interface Architect

191 Altera Corporation; San Jose (CA); On-site; USD 210,000 - 303,000; Full time

Job summary

Altera Corporation in San Jose, CA seeks a Principal High-Speed Interface / Silicon Design Engineer to lead architecture, RTL design, verification, and silicon IP for next-generation FPGA devices. You will own PCIe and related high-speed interfaces, guiding cross-functional teams from architecture through validation.

The role requires deep hands-on RTL with Verilog/SystemVerilog, experience with PAM4/FFE/DFE, PHY/PCS integration, and mentoring of engineers.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 12+ years of experience in ASIC, SoC, FPGA, silicon, or digital IC design.
• 8+ years of experience designing and developing high-speed interface IP or digital subsystems, including RTL in Verilog/SystemVerilog.
• 5+ years of experience with PCI Express, PCIe PHY/PCS, MAC, Link, or related high-speed serial interfaces.
• 3+ years of experience architecting or leading complex silicon IP or subsystem designs.
• 3+ years of experience with high-speed interfaces such as MIPI/MPHY, HDMI, USB, DisplayPort, or similar.
• 3+ years of experience with digital implementation and signoff methodologies (lint, CDC, synthesis, STA, ECD).
• 3+ years of experience with PAM4/FFE/DFE/CDR/LMS and related equalization techniques.

Responsibilities

• Lead the architecture and RTL design of complex high-speed interface IP, focusing on PCIe and related serial tech.
• Provide technical leadership for current and future high-speed interface architectures.
• Define and develop PCIe MAC, PCS, link, and subsystem functionality and control logic.
• Drive end-to-end ownership from architecture through silicon validation.
• Collaborate with PHY designers on requirements, calibration, and system performance.
• Lead design activities involving high-speed equalization and signal processing techniques.
• Address CDC, lint, synthesis, STA, and formal verification issues with teams.
• Work with verification teams to define strategies and drive silicon validation activities.
• Serve as an interface between digital design, PHY/analog, verification, and product engineering.
• Mentor engineers and provide technical direction on architecture and RTL design.
• Lead technical design reviews and influence multi-team decisions.
• Promote continuous improvements in high-speed design methodologies.

Skills

PCI Express

High-speed interfaces

RTL development

Architecture ownership

Mentorship

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Verilog/SystemVerilog

SVA/JasperGold

MATLAB/Simulink

FPGA prototyping

Job description

Altera Corporation in San Jose, CA seeks a Principal High-Speed Interface / Silicon Design Engineer to lead architecture, RTL design, verification, and silicon IP for next-generation FPGA devices. You will own PCIe and related high-speed interfaces, guiding cross-functional teams from architecture through validation.

The role requires deep hands-on RTL with Verilog/SystemVerilog, experience with PAM4/FFE/DFE, PHY/PCS integration, and mentoring of engineers.