Principal NoC IP Micro-Architect

altera; San Jose (CA); On-site; USD 209,500 - 299,200; Full time

Job summary

Altera is seeking a Principal NoC IP Micro‑Architect in San Jose, CA to lead end‑to‑end architecture and RTL design for high‑performance interconnect IPs within next‑generation FPGA platforms. You will collaborate across architecture, design, verification, software, physical design, and product teams to optimize power, performance, area, and reliability.

This senior role requires deep expertise in SoC interconnects, NoC fabrics, performance modeling, and system-level optimization, with a track

Qualifications

• 15+ years of related working experience.
• 10+ years of experience in SystemVerilog, VCS/Synopsys simulators, Lint and synthesis.
• 10+ years of experience in programming with C/C++/Perl/Python/TCL/Unix Shell script.
• 10+ years of experience in FPGA design and programming is a plus.
• 10+ years of experience in RTL validation is a plus.
• 10+ years of experience in development of Network on Chip IPs.
• 5+ years of experience using AI to improve development efficiency is a great plus.

Responsibilities

• Develop logic design, RTL coding, and simulation for Network on Chip IPs and potentially other FPGA IPs & subsystem for integration in full chip designs.
• Participate in the definition of architecture and microarchitecture features of the block being designed.
• Create prototypes, simulate models, and specify system requirements.
• Prepare and design logic diagrams and codes for implementing system design and test specifications.
• Deliver software models for device level bring up, including user visible functionality, timing, and power.
• Apply RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with the physical implementation team.
• Utilize advanced EDA tools such as timing constraints, verification, RTL lint, CDC, RDC & DFT to ensure high quality IP development and deploy automation & AI to enhance development efficiency.
• Review the verification plan and implementation to ensure design features are verified correctly and resolve and implement corrective measures for failing RTL tests to ensure correctness of features.
• As a senior designer, groom next‑level technical members, technically oversee & guide the entire NOC team, and proactively anticipate potential design challenges & roadblocks to take mitigation actions, ensuring successful execution of the SS that meets project requirements and schedule.

Skills

RTL design

NoC IP development

SystemVerilog

verification & lint

C/C++/Python

AI for development

FPGA design

Tools

VCS/Synopsys simulators

Lint

Synthesis

Job description

Job Details:

About Altera
At Altera™, our independence as the world's largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry‑leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster, invest deeper, and partner more closely‑empowering our teams to drive breakthrough innovation and shape the future of the FPGA industry.

About the Role

As a Principal NoC IP Micro‑Architect, you will be responsible for the end‑to‑end architecture, microarchitecture, RTL design, and technical leadership of scalable NoC IP solutions integrated into Altera's next‑generation FPGA platforms. You will work closely with architecture, design, verification, software, physical design, and product teams to deliver high‑performance interconnect solutions optimized for power, performance, area (PPA), scalability, and reliability.

This is a highly visible technical leadership role requiring deep expertise in SoC interconnect architectures, NoC fabrics, RTL development, performance modeling, and system‑level optimization.

Key Responsibilities

• Develop logic design, register transfer level (RTL) coding, and simulation for Network on Chip IPs and potentially other FPGA IPs & subsystem for integration in full chip designs.
• Participate in the definition of architecture and microarchitecture features of the block being designed.
• Create prototypes, simulate models, and specify system requirements.
• Prepare and design logic diagrams and codes for implementing system design and test specifications.
• Deliver software models for device level bring up, including user visible functionality, timing, and power.
• Apply RTL implementation techniques to qualify the design to meet required power, performance, and area goals, partnering with the physical implementation team.
• Utilize advanced EDA tools such as timing constraints, verification, RTL lint, CDC, RDC & DFT to ensure high quality IP development and deploy automation & AI to enhance development efficiency.
• Review the verification plan and implementation to ensure design features are verified correctly and resolve and implement corrective measures for failing RTL tests to ensure correctness of features.
• As a senior designer, groom next‑level technical members, technically oversee & guide the entire NOC team, and proactively anticipate potential design challenges & roadblocks to take mitigation actions, ensuring successful execution of the SS that meets project requirements and schedule.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job‑related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.
$209,500 - $299,200 USD

Qualifications

• Minimum 15+ years of related working experience.
• 10+ years of experience in System Verilog, VCS/Synopsys simulators, Lint and synthesis.
• 10+ years of experience in programming with C/C++/Perl/Python/TCL/Unix Shell script.
• 10+ years of experience in FPGA design and programming is a plus.
• 10+ years of experience in RTL validation is a plus.
• 10+ years of experience in development of Network on Chip IPs.
• 5+ years of experience using AI to improve development efficiency is a great plus.

Job Type

Regular

Shift

Shift 1 (United States of America)

Primary Location

San Jose, California, United States

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.