Senior FPGA Architect: Core Fabric & NoC Innovation

Altera Corporation; San Jose, Northern (CA, KY); Hybrid; USD 149,000 - 215,000; Full time

Job summary

Altera is seeking a Senior FPGA Silicon Design Engineer to drive architecture, design, and verification of next‑generation FPGA circuits and IP. You will own substantial portions of the FPGA fabric, NoC, and interconnect, while mentoring engineers and shaping design methodologies.

You will collaborate across microarchitecture, SoC/full‑chip, RTL, verification, and physical design teams to deliver optimized, power-aware, high‑yield silicon.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or related field with 8+ years FPGA/ASIC design experience.
• 8+ years in FPGA circuit/IP/RTL design and microarchitecture for complex digital systems.
• Strong experience with FPGA fabric, interconnect, routing, clocking, memory blocks, or NoC architectures.

Responsibilities

• Design and develop complex FPGA circuits and IP, including core fabric logic, interconnect and routing, clocking, configuration, memory blocks, and NoC architectures.
• Lead microarchitecture definition and perform circuit and logic design for complex FPGA blocks and subsystems, optimizing power, performance, area, timing, reliability, and yield.
• Develop schematics, RTL implementations, behavioral models, and simulations to evaluate and validate FPGA architectures and capabilities.
• Perform functional and reliability verification of FPGA circuits and IP, working with verification teams to debug and resolve issues.
• Develop and maintain design models and collateral to integrate FPGA circuits and IP into hardware and software deliverables.
• Drive improvements to meet aggressive PPA targets and integrate FPGA IP into larger systems.

Skills

FPGA design

RTL design

Microarchitecture

Hardware verification

Power/Performance optimization

Education

Bachelor's degree in Electrical Engineering

Tools

FPGA design tools

Job description

Altera is seeking a Senior FPGA Silicon Design Engineer to drive architecture, design, and verification of next‑generation FPGA circuits and IP. You will own substantial portions of the FPGA fabric, NoC, and interconnect, while mentoring engineers and shaping design methodologies.

You will collaborate across microarchitecture, SoC/full‑chip, RTL, verification, and physical design teams to deliver optimized, power-aware, high‑yield silicon.