Principal Memory Architect for AI/ML Accelerators

Broadcom; San Jose (CA); On-site; USD 200,000 - 320,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grants

401(k) matching

Job summary

Broadcom in San Jose invites you to lead memory subsystem and data transport architecture for AI/ML accelerators. Own end-to-end path from memory tech through controller, on-die network, DMA engines, and scratchpads, across multiple silicon generations with power-performance trade-offs.

You will model, simulate, and influence choices with internal teams and memory/IP vendors, delivering scalable solutions that meet AI workloads demands for latency and bandwidth.

Qualifications

• 18+ years in ASIC/SoC architecture focused on memory systems and data movement for HPC or AI.
• Deep knowledge of memory subsystems: HBM, DDR/LPDDR/GDDR, controller architecture, cache coherency and memory consistency models.
• Ownership of a data movement architecture — on-die interconnect, DMA/copy engines, buffer hierarchies, and knowledge of costs for NVLink, UALink, RDMA, ARM CHI, UCIe, PCIe.
• Strong performance modeling and system-level simulation; command of latency, throughput, utilization, and scalability.

Responsibilities

• Define end-to-end memory and data transport architecture for accelerators — from memory technology through the controller, on-die network, and DMA engines to scratchpads.
• Own memory architecture roadmap and energy-efficient interconnect design across multiple silicon generations.
• Perform modeling, simulation, and silicon realization with quantified confidence.

Skills

MSEE/MSCE/PhD

18+ yrs ASIC/SoC

Memory systems expertise

Data movement architecture

Education

MSEE/MSCE or PhD in EE/CE/CS

Job description

Broadcom in San Jose invites you to lead memory subsystem and data transport architecture for AI/ML accelerators. Own end-to-end path from memory tech through controller, on-die network, DMA engines, and scratchpads, across multiple silicon generations with power-performance trade-offs.

You will model, simulate, and influence choices with internal teams and memory/IP vendors, delivering scalable solutions that meet AI workloads demands for latency and bandwidth.