# AI/ML Silicon Accelerator Memory Architect

8224 Avago Technologies Wireless (U.S.A.) Manufacturing LLC; San Jose (CA); On-site; USD 200,000 - 320,000; Full time

Benefits offered by this job

Medical plans

401K match

ESPP

Job summary

Broadcom, Inc. in California seeks a Principal Architect/Distinguished Architect to own memory architecture and data transport for AI accelerators.

You will define end-to-end memory strategy, memory controllers, on-die interconnects, and DMA engines across multiple silicon generations, balancing performance and power. Lead modeling and silicon realization with first-principles analysis, collaborating with internal teams and external memory/IP vendors to optimize latency, bandwidth and energy

Qualifications

• 18+ years in ASIC/SoC memory systems and data movement.
• Deep knowledge of memory subsystems: HBM, DDR/LPDDR/GDDR.
• Ownership of data movement architecture including on-die interconnect.

Responsibilities

• Own memory architecture and roadmap across multiple silicon generations.
• Oversee data transport path from memory to MACs, including DMA engines.
• Model and verify performance, latency, and energy trade-offs.
• Collaborate with internal teams and memory/IP vendors.

Skills

Memory systems

On-die interconnect

DMA engines

Performance modeling

System-level simulation

Latency analysis

Education

MSEE/MSCE or PhD in EE/CE/CS

Tools

NVLink

UALink

RDMA

ARM CHI

UCIe

PCIe

Job description

Job Description:

Memory Subsystems and Low-Power Data Transport

Level: Principal Architect/Distinguished Architect

Function: Silicon Architecture — AI/ML Accelerators

The Role

You will define the end-to-end memory *and* data transport architecture for our accelerators — from the memory technology we bet on, through the controller, on-die network, and DMA engines, all the way into the scratchpads feeding the compute blocks.

This is not a "pick the DRAM generation" role.

It is ownership of the whole data path across multiple silicon generations, including the performance-versus-power analysis that decides major trade-offs and the co-architecture with internal teams and external memory/IP vendors.

What You'll Own

Memory architecture and roadmap. Multi-generation memory strategy across the portfolio — HBM, LPDDR/GDDR/DDR, on-die SRAM hierarchies and scratchpads. Capacity, bandwidth, and latency requirements derived from real AI workloads (model size, KV-cache growth, prefill versus decode, MoE sparsity). Memory controller and cache/scratchpad microarchitecture: scheduling, address mapping, QoS across compute, DMA, and host traffic.

Data transport and energy-efficient movement. The complete path from memory to the MACs: on-die interconnect (topology, flow control, deadlock avoidance, QoS under mixed traffic), and the DMA, gather/scatter, layout-transform, and multicast engines that make it usable. You own the pJ/bit budget as a first-class constraint.

Modeling and silicon realization. Analytical and simulation-based models that make architectural calls with quantified confidence.

Minimum Qualifications

• MSEE/MSCE or PhD in EE, CE, CS, or related field, or equivalent demonstrated architectural impact.
• 18+ years in ASIC/SoC architecture focused on memory systems and data movement for HPC or AI. Deep knowledge of memory subsystems: HBM, DDR/LPDDR/GDDR, controller architecture, cache coherency and memory consistency models, tiered and pooled memory.
• Demonstrated ownership of a data movement architecture — on-die interconnect, DMA/copy engines, buffer hierarchies, and the dataflow connecting them to compute — including what each protocol (NVLink, UALink, RDMA, ARM CHI, UCIe, PCIe) actually costs in latency, area, and power.
• Strong performance modeling and system-level simulation background; first-principles command of latency, throughput, utilization, and scalability.

Compensation and Benefits

The annual base salary range for this position is USD 200,000.00 To USD 320,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Welcome! Thank you for your interest in Broadcom! We are a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions. For more information please visit our video library and check out our Connected by Broadcom series. Follow us on Linked In Broadcom Inc.