AI Accelerator Memory Architect: End-to-End Dataflow

Broadcom, Inc.; San Jose (CA); On-site; USD 200,000 - 320,000; Full time

Benefits offered by this job

Medical plans

401K match

ESPP

Job summary

Broadcom, Inc. in California seeks a Principal Architect/Distinguished Architect to own memory architecture and data transport for AI accelerators.

You will define end-to-end memory strategy, memory controllers, on-die interconnects, and DMA engines across multiple silicon generations, balancing performance and power. Lead modeling and silicon realization with first-principles analysis, collaborating with internal teams and external memory/IP vendors to optimize latency, bandwidth and energy

Qualifications

• 18+ years in ASIC/SoC memory systems and data movement.
• Deep knowledge of memory subsystems: HBM, DDR/LPDDR/GDDR.
• Ownership of data movement architecture including on-die interconnect.

Responsibilities

• Own memory architecture and roadmap across multiple silicon generations.
• Oversee data transport path from memory to MACs, including DMA engines.
• Model and verify performance, latency, and energy trade-offs.
• Collaborate with internal teams and memory/IP vendors.

Skills

Memory systems

On-die interconnect

DMA engines

Performance modeling

System-level simulation

Latency analysis

Education

MSEE/MSCE or PhD in EE/CE/CS

Tools

NVLink

UALink

RDMA

ARM CHI

UCIe

PCIe

Job description

Broadcom, Inc. in California seeks a Principal Architect/Distinguished Architect to own memory architecture and data transport for AI accelerators.

You will define end-to-end memory strategy, memory controllers, on-die interconnects, and DMA engines across multiple silicon generations, balancing performance and power. Lead modeling and silicon realization with first-principles analysis, collaborating with internal teams and external memory/IP vendors to optimize latency, bandwidth and energy