Expert/Senior Logic Design Engineer (Fully Remote)

Confidential Client; United States; Remote; USD 120,000 - 180,000; Full time

Job summary

Confidential Client seeks an experienced FPGA/ASIC Design Engineer to design low-latency RTL in SystemVerilog and develop signal-processing logic for real-time control.

You will own the RTL lifecycle from architecture through verification, collaborating with hardware and software teams in an international engineering environment focused on FPGA/ASIC platforms.

Qualifications

• BS/MS in EE/CE or equivalent, 4+ years FPGA/ASIC design.
• Strong SystemVerilog and microarchitecture skills.
• Experience with synthesis, STA, and CDC.

Responsibilities

• Design and implement low-latency RTL modules in SystemVerilog.
• Develop FPGA/ASIC logic for signal processing and real-time control.
• Own RTL lifecycle from architecture to verification.

Skills

SystemVerilog

Microarchitecture

Education

BS/MS in EE/CE or equivalent

Job description

• Design and implement low-latency RTL modules in SystemVerilog.
• Develop FPGA/ASIC logic for signal processing and real-time control.
• Own RTL lifecycle from architecture to verification.

Requirements:

• BS/MS in EE/CE or equivalent, 4+ years FPGA/ASIC design.
• Strong SystemVerilog and microarchitecture skills.
• Experience with synthesis, STA, and CDC.

Nice to Have:

• Familiarity with AXI, PCIe, DDR interfaces.
• Python/Tcl scripting.

Confidential Client

The company develops advanced control and measurement systems for quantum computing, enabling precise real-time control of complex quantum systems. It works in an international engineering environment focused on FPGA and ASIC-based platforms.