Principal Logic Design Engineer

Protingent; Hillsboro (OR); Hybrid; USD 127,000 - 237,000; Full time

Job summary

Protingent Staffing seeks a Principal Logic Design Engineer for a Direct Hire role in Hillsboro, OR or San Jose, CA. You will own micro-architecture and RTL design for critical blocks and collaborate with verification and physical design teams to optimize performance and timing.

The ideal candidate has 10+ years of ASIC/FPGA logic design with a BSEE (or 8+ years with an MSEE) and strong SystemVerilog RTL plus simulator experience. This hybrid role involves onsite and remote collaboration.

Qualifications

• 10+ years of logic design experience (ASIC/FPGA) with BSEE, or 8+ years with MSEE.
• Strong SystemVerilog/Verilog RTL design expertise.
• Experience with simulators Questa/Incisive/VCS.
• Scripting experience in Python/Perl/TCL.
• Ability to learn quickly and work independently.
• Solid communication and project management skills.

Responsibilities

• Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces.
• Analyze performance, power, and area trade-offs and drive design decisions based on quantitative data.
• Collaborate with verification team to shape test plans and improve verification coverage.
• Work with physical design team to resolve timing, power, and congestion challenges.
• Work with verification team on regression failure debug and provide RTL fixes.
• Provide technical support to FAE team on pre-sales customer engagements.
• Provide technical support to AE team on post-sales customer deliveries.

Skills

SystemVerilog RTL design

Verilog RTL

Python scripting

Perl scripting

TCL scripting

Communication

Project management

Independent work

Education

BSEE

MSEE

Tools

Questa

Incisive

VCS

Job description

Position Title: Principal Logic Design Engineer Position Description: Protingent Staffing has an exciting Direct Hire opportunity for a Principal Logic Design Engineer with our client in Hillsboro, OR and San Jose, CA.

Job Responsibilities

• Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces
• Analyze performance, power, and area (PPA) trade-offs and drive design decisions based on quantitative data
• Collaborate closely with verification team to shape test plans and improve verification coverage
• Work with physical design team to understand and resolve timing, power, and congestion challenges
• Work with verification team on regression failure debug and root cause, and provide RTL fix if necessary
• Provide technical support to FAE team on pre-sales customer engagements
• Provide technical support to AE team on post-sales customer deliveries

Job Qualifications

• Strong System Verilog/Verilog RTL design expertise
• Questa/Incisive/VCS simulator experience
• Python/Perl/TCL scripting experience.
• Ability to learn quickly and work independently
• Solid communication and project management skills
• 10+ years of logic design experience (ASIC/FPGA) with BSEE, or 8+ years of logic design experience (ASIC/FPGA) with MSEE.

Preferred Job Qualifications

• ASIC synthesis, timing constraint, CDC/RDC experience
• UVM Verification experience
• Memory (HBM, LPDDR) expertise
• AMBA AXI or CHI design experience

Job Details

• Job Type: Direct Hire
• Location: Hillsboro, OR or San Jose, CA (Hybrid 3 days a week onsite)
• Salary Range Rate: $127,400 to $236,600.

About Protingent

Protingent is an award-winning provider of top-tier Engineering and IT talent, trusted by companies at the forefront of innovation—from Software and Aerospace to AI, Clean Tech, Medical Devices, and Connected Technologies. We're passionate about connecting exceptional talent with meaningful opportunities and helping our clients build the future.