PE Logic Design

Rambus.com; Hillsboro (OR); Hybrid; USD 127,000 - 237,000; Full time

Benefits offered by this job

Hybrid work model

Competitive compensation package

Job summary

Rambus, a leading memory interface and silicon IP company, seeks a Principal Logic Design Engineer to join the Silicon IP team in Hillsboro, Oregon. You will contribute to micro-architecture and RTL design of high‑performance memory controllers for data centers and AI applications, reporting to the Director of Engineering as an individual contributor.

The role requires deep SystemVerilog/Verilog expertise, strong design and verification skills, and the ability to work across design, verification

Qualifications

• Strong SystemVerilog/Verilog RTL design expertise.
• Questa/Incisive/VCS simulator experience.
• Python/Perl/TCL scripting experience.
• Ability to learn quickly and work independently.
• Solid communication and project management skills.
• 10+ years of logic design experience (ASIC/FPGA) with BSEE, or 8+ years with MSEE.

Responsibilities

• Own micro-architecture definition and RTL design for critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces.
• Analyze performance, power, and area (PPA) trade-offs and drive design decisions based on quantitative data.
• Collaborate closely with verification team to shape test plans and improve verification coverage.
• Work with physical-design team to understand and resolve timing, power, and congestion challenges.
• Work with verification team on regression failure debug and root cause, and provide RTL fixes if necessary.
• Provide technical support to FAE team on pre-sales customer engagements.
• Provide technical support to AE team on post-sales customer deliveries.

Skills

SystemVerilog/Verilog RTL design

Questa/Incisive/VCS

Python/Perl/TCL scripting

ASIC/FPGA design experience

Communication & project management

AMBA AXI/CHI design

Memory (HBM/LPDDR) expertise

Education

BSEE

MSEE

Tools

Questa/Incisive/VCS

Job description

Overview

Rambus, a premier chip and silicon IP provider,is seekingto hirean exceptionalPrincipalLogic Design Engineerto joinourSilicon IP (SIP)teaminHillsboro, Oregon.Candidates will be joiningsome of the brightest inventors and engineers in the world to develop productsthat make data faster and safer.

In this role, the candidate will be reporting to the Director of Engineering as an individual contributor.As aPrincipal Logic Design Engineer, youwill play a pivotal role inthemicro-architecture anddesign of ournext-generationhigh performance andcutting-edgememory controllers for data centers and AI applications.This is a fast-growing market with high demand from tier-1 customers which gives ample opportunity for innovation and differentiation. If you like challenges and want to make a technical difference in the memory landscape during these exciting times in the semiconductor industry, this is the right opportunity for you.

Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.

Responsibilities

• Ownmicro-architecturedefinitionand RTL designfor critical blocks such as schedulers, command pipelines, coherency/ordering logic and system interfaces

• Analyze performance, power, and area (PPA) trade-offs and drive design decisions based on quantitativedata

• Collaborate closely withverificationteam to shape test plans and improve verification coverage

• Work withphysicaldesign team to understand and resolve timing, power, and congestion challenges

• Work withverification team onregression failure debugand root cause, and provide RTL fixif necessary

• Providetechnicalsupport to FAE team onpre-sales customer engagements

• Providetechnicalsupport to AE team onpost-salescustomer deliveries

Qualifications

• Strong System Verilog/Verilog RTL design expertise

• Questa/Incisive/VCS simulator experience

• Python/Perl/TCLscripting experience

• Ability to learn quickly and work independently

• Solid communication and project management skills

• 10+ years of logic design experience(ASIC/FPGA)with BSEE, or

• 8+ years of logic designexperience(ASIC/FPGA)with MSEE

Definite Plus:

• ASIC synthesis, timing constraint, CDC/RDC experience

• UVMVerification experience

• Memory (HBM, LPDDR) expertise

• AMBA AXI or CHI design experience

About Rambus

Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing. With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads. Our world-class team is the foundation of our company, and our innovative spirit drives us to develop thecutting-edgeproducts and technologies essential for tomorrow’s systems.

Rambus offers a competitive compensation packageincludingbase salary, bonus, equity, matching 401(k), employee stock purchase plan, comprehensive medical and dental benefits, time-off program, and gym membership.

TheUSsalary range for thisfull-timeposition is $127,400to $236,600.Our salary ranges aredeterminedby role,leveland location. The successful candidate’s starting pay will bedeterminedbased on job-related skills, experience, qualifications, worklocationand market conditions.

At Rambus, we are committed to fostering a workplace where every individual is respected, supported, and empowered to succeed. We value a range of perspectives and experiences that contribute to innovation and collaboration. Our goal is to ensure that all team members haveequitableaccess to opportunities, resources, and a sense of belonging. We believe that a culture of fairness and inclusion helps us all do ourbest work.

Rambus is proud to be an Equal Employment Opportunity and Affiantive Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics.

Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veteransduringour job application procedures. If yourequireassistanceoran accommodationdue to a disability,please feel free to inform us in your application.

Rambus does not accept unsolicited resumes from headhunters, recruitmentagenciesor fee-based recruitment services.

For more information about Rambus, visit rambus.com. Foradditionalinformation on life at Rambus and our current openings, check outrambus.com/careers/.

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