Principal IO/Clocking Design Engineer

Micron Memory Malaysia Sdn Bhd; Boise (ID); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Paid time off

Paid holidays

401(k) plan

Job summary

Micron Technology in Boise, Idaho seeks a Principal IO/Clocking Design Engineer to lead development and verification of high-speed IO and clocking circuits for DRAM products. You will push performance, analyze impairments, and ensure timing budgets across projects.

You will collaborate with Product Engineering, SI, and process teams, and mentor engineers while contributing to modeling, simulation, and silicon validation. Seniority and strong Unix/Cadence skills are preferred.

Qualifications

• Minimum MSEE with 10+ years’ analog/mixed-signal design experience.
• Ability to supervise layout and ensure good high-speed layout practices.
• Proficiency with UNIX and Cadence design environment.
• Strong communication skills and ability to convey technical concepts to peers.

Responsibilities

• Innovate, design, optimize and verify high-speed IO and clocking circuits for DRAM products.
• Apply high-speed circuit design techniques and evaluate IO/clocking performance at circuit level.
• Develop modeling, analysis and simulation methodology for full-chip and system-level impact.
• Collaborate with Product Engineering and SI teams to compare silicon performance with simulations.
• Mentor engineers and support silicon validation efforts across projects.

Skills

High-speed IO

Clocking design

Cadence

Unix

Python scripting

Team leadership

Modeling

Education

MSEE

BSEE

Tools

Cadence

UNIX

SPF extraction

Job description

Micron Technology in Boise, Idaho seeks a Principal IO/Clocking Design Engineer to lead development and verification of high-speed IO and clocking circuits for DRAM products. You will push performance, analyze impairments, and ensure timing budgets across projects.

You will collaborate with Product Engineering, SI, and process teams, and mentor engineers while contributing to modeling, simulation, and silicon validation. Seniority and strong Unix/Cadence skills are preferred.