Lead IO & Clocking Design Engineer (High‑Speed DRAM)

Micron Technology, Inc; Boise (ID); On-site; USD 120,000 - 150,000; Full time

Job summary

Micron Technology, Inc is seeking a Principal IO Design Engineer in Boise, Idaho. You will innovate, design, optimize, and verify high-speed IO circuits for DRAM products. The role demands extensive experience in analog and mixed-signal circuit design.

Candidates should have strong technical communication skills and the ability to work collaboratively across various teams. Relocation assistance information is to be determined.

Qualifications

• Minimum MSEE + 10 years or BSEE + 12 years of experience in analog and mixed‑signal circuit design.
• Proficiency with UNIX and CADENCE design environment.
• Understanding of device physics and basic CMOS processing techniques.
• Ability to supervise layout work and understand good layout practices.
• Strong communication skills to convey technical concepts.
• Mental agility to work with various product types and teams.

Responsibilities

• Innovate, design, optimize and verify high‑speed IO and clocking circuits.
• Develop modeling, analysis and simulation methodology.
• Work with engineering teams to compare silicon performance with simulation results.
• Collaborate on Micron's next groundbreaking process node.

Skills

Analog circuit design

Mixed-signal circuit design

High-speed circuit optimization

Communication skills

Scripting languages (PERL/Python)

Education

MSEE + 10 years or BSEE + 12 years of experience

Tools

UNIX

CADENCE

Job description

Micron Technology, Inc is seeking a Principal IO Design Engineer in Boise, Idaho. You will innovate, design, optimize, and verify high-speed IO circuits for DRAM products. The role demands extensive experience in analog and mixed-signal circuit design.

Candidates should have strong technical communication skills and the ability to work collaboratively across various teams. Relocation assistance information is to be determined.