Principal Engineer – Physical Design

FHLB Des Moines; Chandler, Northern (AZ, KY); Hybrid; USD 140,000 - 190,000; Full time

Job summary

Microchip Technology Inc is seeking a Principal Engineer to own full-chip APR and physical implementation, including netlist-to-GDSII, for advanced designs in Chandler, AZ. This role demands 10+ years of hands-on physical design experience across floorplanning, placement, clock-tree synthesis, routing, and sign-off.

You will lead cross-functional activities with a worldwide PD team, using ICC/ICC2 or Innovus and UPF low-power practices.

Qualifications

• Bachelor’s or Masters Degree in Electrical / Electronics Engineering with 10+ years of relevant experience.
• Hands-on experience in physical design flows such as floor planning, placement optimization.
• Clock tree synthesis, routing, crosstalk avoidance and physical verification experience.
• Advanced knowledge of place and route methodologies and timing closure.
• Experience with full chip Physical Design activities and sign-off tools.
• Knowledge of UPF and Low Power design practices throughout the flow.
• Proficiency in Tcl and Perl scripting.
• Excellent communication and problem-solving skills.
• Self-motivated team player with collaboration across globally distributed teams.

Responsibilities

• Lead full Chip APR and Physical Implementation (Netlist-to-GDSII).
• Collaborate with global teams across design groups to meet goals.
• Develop and optimize floorplanning, placement, and routing strategies.
• Ensure timing closure and design sign-off across multiple tech nodes.
• Mentor engineers and improve PD flows and methodologies.

Skills

Floor planning

Placement optimization

Clock tree synthesis

Routing

Crosstalk avoidance

Physical verification

VLSI timing closure

Tcl scripting

Perl scripting

Team collaboration

Problem solving

Education

Electrical/Electronics Engineering degree (Bachelor or Master)

Tools

ICC/ICC2

Innovus

Parasitic Extraction

Sign-off tools

Job description

## Principal Engineer – Physical DesignApplylocations: AZ - Chandlertime type: Full timeposted on: Posted Yesterdayjob requisition id: R1990-26Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the *Aggregate System* and it’s won us countless awards for diversity and workplace excellence.Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.Visit our careers page to see what exciting opportunities and company perks await!**Job Description:**Microchip’s CAD Physical Design (PD) team is looking for a Principal Engineer to work on Full Chip APR/Physical Implementation (Netlist-to-GDSII). In this role you will be working as part of a worldwide team in all areas of Physical Implementation including APR of hierarchical, low power, multi-mode, multi corner mixed signal designs.**Requirements/Qualifications:*** Bachelor’s or Masters Degree in Electrical / Electronics Engineering with 10+ years of relevant experience* Hands-on experience in all aspects of physical design flows such as floor planning, placement optimization,* clock tree synthesis, routing, crosstalk avoidance and physical verification* Advanced knowledge of place and route methodologies.* Recent experience with leading full chip Physical Design activities.* Advanced knowledge of VLSI logic principles, clock structures, and design timing closure.* Advanced knowledge of sign-off tools for Static Timing Analysis, Formal Equivalence, Parasitic Extraction,* Power Integrity, and Physical Verification is required* Knowledge of and experience in UPF and Low Power design practices throughout entire physical design flow.* Daily use of ICC/ICC2 or Innovus is preferred.* Experience with 40nm or 28nm technologies is required, 16nm or smaller technology preferred* Proficiency in Tcl and Perl scripting is essential.* Excellent written and verbal communication skills.* Excellent problem-solving and debugging skills.* Self-motivated team player that can collaborate with multiple teams across a geographically diverse* company to achieve desired design goals is crucial.**Travel Time:**0% - 25%**Physical Attributes:**Hearing, Seeing, Talking, Works Alone, Works Around Others**Physical Requirements:**80% sitting, 10% walking, 10% standingMicrochip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.**To all recruitment agencies**: *Microchip Technology Inc. **does not** accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.*