Director, Verification

Kepler Computing; San Jose (CA); On-site; USD 270,000 - 310,000; Full time

Job summary

Kepler Computing seeks a seasoned Director of Verification to own pre-silicon verification and post-silicon validation for its products. This role blends architecture, design and software, demanding deep VLSI verification expertise and proven team leadership.

You will drive end-to-end verification programs from definition through tapeout and post-silicon bring-up, building VIPs and a robust regression framework while mentoring a high-performing team.

Qualifications

• 15+ years of hands-on VLSI front-end verification experience with multiple successful SoC/ASIC tapeouts.
• Deep expertise in UVM-based verification: testbench architecture, scoreboarding, coverage modeling.

Responsibilities

• Own the end-to-end pre-silicon verification strategy: test plans, testbench development, automated flows and regressions, coverage closure and tapeout signoff.
• Define and run a comprehensive verification plan: functional coverage, assertion-based verification, constrained-random stimulus, formal verification and AI-assisted flows.
• Co‑lead model‑based testing, emulation and FPGA prototyping for pre‑silicon verification, software development and architectural validation.
• Work with architecture, RTL design, DFD and software teams to align verification plans with design intent.
• Define and run post‑silicon bring‑up, validation, debug and production qualification.
• Develop verification IP (VIP) and protocol checkers.
• Set UVM‑based testbench architecture standards and a coverage‑driven verification methodology.
• Build and maintain regression infrastructure: nightly and weekly pipelines, coverage merge and automated triage.
• Track and publish verification health metrics (coverage, assertion density, regression health) and run regular milestone reviews.
• Build, lead and mentor a team of verification and emulation engineers.

Skills

VLSI verification

UVM-based verification

SystemVerilog

SoC/ASIC tapeouts

leadership

Education

B.Tech/M.Tech/MS in EE/ Electronics/VLSI

Tools

None

Job description

About The Role

We’re looking for a highly experienced Director, Verification to own pre-silicon verification and post-silicon validation for Kepler’s products. This high-impact leadership role sits where architecture, design and software meet. It calls for deep VLSI verification expertise and the ability to build and inspire high-performing teams. You’ll drive complex verification programs from early definition through product development, tapeout and post-silicon bring‑up and validation.

Responsibilities

• Own the end-to-end pre-silicon verification strategy: test plans, testbench development, automated flows and regressions, coverage closure and tapeout signoff.
• Define and run a comprehensive verification plan: functional coverage, assertion-based verification, constrained-random stimulus, formal verification and AI-assisted flows.
• Co‑lead model‑based testing, emulation and FPGA prototyping for pre‑silicon verification, software development and architectural validation.
• Work with architecture, RTL design, DFD and software teams to align verification plans with design intent.
• Define and run post‑silicon bring‑up, validation, debug and production qualification.
• Develop verification IP (VIP) and protocol checkers.
• Set UVM‑based testbench architecture standards and a coverage‑driven verification methodology.
• Build and maintain regression infrastructure: nightly and weekly pipelines, coverage merge and automated triage.
• Track and publish verification health metrics (coverage, assertion density, regression health) and run regular milestone reviews.
• Build, lead and mentor a team of verification and emulation engineers.

Requirements

• B.Tech/M.Tech/MS in EE, Electronics, VLSI Design or a related field.
• 15+ years of hands‑on VLSI front‑end verification experience with multiple successful SoC/ASIC tapeouts.
• Deep expertise in UVM-based verification: testbench architecture, scoreboarding, coverage modeling and constrained-random verification.
• Strong SystemVerilog skills: interfaces, clocking blocks, SVA, covergroups and testbenches.
• Thorough understanding of SoC-level verification challenges: CDC, power‑aware verification (UPF), memory subsystems, and interrupt and reset validation.
• Solid knowledge of industry‑standard on‑chip and memory protocols and VIP integration.
• Hands‑on experience with industry-standard formal verification and simulation tools.
• Hands‑on experience with coverage closure: functional, code and assertion coverage.
• Good scripting skills (Python, Perl, Shell, Makefile).
• Exposure to hardware/software co‑verification (TLM/SystemC).
• Experience with post‑silicon validation, debug and production test correlation.
• Excellent leadership and communication skills, with a proven ability to lead teams in a fast‑paced environment.
• Proven record from pre‑silicon verification through production release.

Nice to Have

• Experience with emulation platforms.
• Familiarity with ML-assisted verification such as coverage prediction and test prioritization.
• Understanding of DFT-aware verification (scan, BIST, JTAG) and debug architecture.
• Knowledge of verification challenges in 3D innovations.
• Familiarity with AI workloads and their memory demands.
• Prior startup experience with lean teams and aggressive timelines.

Compensation And Benefits

Actual compensation will be determined based on factors including, but not limited to, relevant experience, skills, qualifications, education, job responsibilities and work location.

Kepler offers a comprehensive benefits package to eligible employees, including medical, dental and vision coverage, retirement benefits, time off and additional Kepler benefits as applicable. Eligibility and benefit offerings may vary based on employment status and work location.

Equal Employment Opportunity

Kepler is an Equal Opportunity Employer. We provide equal employment opportunities to all applicants and employees and do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, or any other characteristic protected under applicable federal, state, or local law.

We believe that different backgrounds, experiences, perspectives and ideas make our team stronger and help our employees, our technology and our community thrive.

Reasonable Accommodation

Kepler is committed to providing reasonable accommodations to qualified individuals with disabilities throughout the application and hiring process. If you need a reasonable accommodation to participate in the application or interview process, please contact us at 408-365-4627 or [e-mail].

Fair Chance Hiring

Kepler will consider qualified applicants with criminal histories in accordance with applicable federal, state, and local laws, including the California Fair Chance Act. Applicants are not required to disclose criminal history before a conditional offer of employment except where otherwise permitted or required by applicable law.

Federal Contractor Notice

Kepler is a federal contractor or subcontractor and is committed to its obligations regarding equal employment opportunity. Kepler does not discriminate against qualified individuals on the basis of disability or protected veteran status and takes steps to employ and advance in employment qualified individuals with disabilities and protected veterans.

Compensation Range: $270K - $310K