DFT Lead

Insight Global (United States); San Jose (CA); On-site; USD 150,000 - 230,000; Full time

Job summary

Insight Global is seeking an experienced Hardware DFT engineer in San Jose, CA. You will implement scan, mbist, BISR and boundary scan, and support post-silicon testing and debugging.

You will collaborate with RTL, analog/mixed-signal, and test teams to design reusable DFT IP and drive full-chip integration with testability features for high-volume production.

Qualifications

• Degree in Electrical or Computer Engineering required with 8–10 years of experience.
• Experience with JTAG, scan, BIST architectures and boundary scan.
• Hands-on post-silicon debug of DFT patterns (scan/mbist/boundary scan).
• Ability to learn new concepts and mentor teams in DFT methodologies.
• Excellent communication and presentation skills.

Responsibilities

• Implement DFT features: scan, mbist, BISR, boundary scan and DFT simulations.
• Support post-silicon testing and debugging with minimal mentorship.
• Develop innovative DFT IP and integrate with RTL for full chip design.
• Collaborate with multi-functional teams on silicon testability strategies.

Skills

JTAG protocols

Scan architecture

BIST architectures

Memory BIST

Boundary scan

High-speed macros

ATPG

Tessent

Xcelium

Genus

Tempus/Primetime

Post-silicon debug

DFT methodologies

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

Tessent

Xcelium

Genus

Tempus/Primetime

Job description

Candidate Responsibilities:

• Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debug

• Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.

• Along with the DFT team, you will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.

• The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.

Skills and Requirements

1.Bachelor's or a Master's Degree in Electrical or Computer Engineering required, with at least 8-10 years of experience.

1. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and integrating 3rd party IP’s and high speed digital/analog macros

2. Experience with ATPG and EDA tools like Tessent tool sets, Xcelium, Genus, Tempus/Primetime

3. At least one project with hands-on post-silicon debug of DFT patterns - scan, mbist, boundary scan and release to productionStrong ability to establish/refine, train teams on DFT methodologies - from design phase to high volume production

4. Ability to quickly learn new concepts and adapt to evolving technologies

5. Excellent communication and presentation skills

6. Strong attention to detail and system level understanding of networking and photonic solutions

We are a company committed to creating diverse and inclusive environments where people can bring their full, authentic selves to work every day. We are an equal employment opportunity/affirmative action employer that believes everyone matters. Qualified candidates will receive consideration for employment without regard to race, color, ethnicity, religion, sex (including pregnancy), sexual orientation, gender identity and expression, marital status, national origin, ancestry, genetic factors, age, disability, protected veteran status, military or uniformed service member status, or any other status or characteristic protected by applicable laws, regulations, and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request to [e-mail].