Director, Memory Design

Kepler Computing; San Jose (CA); On-site; USD 270,000 - 310,000; Full time

Job summary

Kepler is seeking a technically deep Director, Memory Design to own memory controller design for Kepler’s memory products. The role sits where memory architecture, digital logic design and system integration meet, requiring hands-on expertise in memory controller architecture, RTL design, and AI workload optimization.

You will lead end-to-end design efforts from architecture to tapeout, drive PPA optimization, and collaborate with architecture, physical design and post-silicon validation teams.

Qualifications

• 15+ years in memory controller architecture and RTL design
• Expert knowledge of memory controller design: scheduling, ECC, refresh, power management and training
• Strong understanding of industry-standard memory protocols and VLSI trade-offs across latency, bandwidth, power and area
• SystemVerilog, front-end flows (synthesis, CDC, formal verification) and scripting (Python, Perl, Tcl)
• Experience with memory controller performance modeling: simulation, queue-depth analysis and scheduler evaluation
• Deep hands-on timing closure experience on complex, high-frequency digital blocks
• Proven record of leading design teams through at least three full-chip tapeouts in advanced process technologies
• Proven ability to work across teams and deliver complex design blocks with small teams

Responsibilities

• Own memory controller design end to end, from architecture to tapeout, including low-latency memory access paths and high-bandwidth interfaces
• Write and maintain high-quality SystemVerilog RTL. Drive PPA optimization and implementation convergence (lint, CDC/RDC, LEC, synthesis, timing closure)
• Define and review functional and formal verification plans, validate SDC timing constraints, and ensure design quality through rigorous reviews
• Work closely with architecture, physical design and post-silicon validation teams
• Lead the investigation and fixing of complex timing violations and structural design issues during physical implementation
• Define and drive adoption of new design methods that improve power efficiency in high-bandwidth memory interfaces
• Set design best practices, keep technical documentation current, and mentor engineers

Skills

Memory architecture

RTL design

Team leadership

Tapeouts

Education

B.Tech/M.Tech/MS/PhD in Electrical/Computer Engineering

Tools

SystemVerilog

Synthesis

CDC

Formal verification

Python

Perl

Tcl

Job description

About The Role

We’re looking for a technically deep Director, Memory Design to own memory controller design for Kepler’s memory products. The role sits where memory architecture, digital logic design and system integration meet. You’ll bring hands‑on expertise in memory controller architecture and RTL design, low‑latency access path design and memory subsystem optimization for AI workloads. You’ll both architect and implement, making sound VLSI trade-offs throughout.

About The Role

We’re looking for a technically deep Director, Memory Design to own memory controller design for Kepler’s memory products. The role sits where memory architecture, digital logic design and system integration meet. You’ll bring hands‑on expertise in memory controller architecture and RTL design, low‑latency access path design and memory subsystem optimization for AI workloads. You’ll both architect and implement, making sound VLSI trade-offs throughout.

Key Responsibilities

• Own memory controller design end to end, from architecture to tapeout, including low‑latency memory access paths and high‑bandwidth interfaces.
• Write and maintain high‑quality SystemVerilog RTL. Drive PPA optimization and implementation convergence (lint, CDC/RDC, LEC, synthesis, timing closure).
• Define and review functional and formal verification plans, validate SDC timing constraints, and ensure design quality through rigorous reviews.
• Work closely with architecture, physical design and post‑silicon validation teams.
• Lead the investigation and fixing of complex timing violations and structural design issues during physical implementation.
• Define and drive adoption of new design methods that improve power efficiency in high‑bandwidth memory interfaces.
• Set design best practices, keep technical documentation current, and mentor engineers.

Requirements

• B.Tech/M.Tech/MS/PhD in Electrical/Computer Engineering or a related field.
• 15+ years in memory controller architecture and RTL design, including multiple successful SoC tapeouts.
• Expert knowledge of memory controller design: scheduling, ECC, refresh, power management and training.
• Strong understanding of industry‑standard memory protocols and VLSI trade‑offs across latency, bandwidth, power and area.
• Skilled in SystemVerilog, front‑end flows (synthesis, CDC, formal verification) and scripting (Python, Perl, Tcl).
• Experience with memory controller performance modeling: simulation, queue‑depth analysis and scheduler evaluation.
• Deep hands‑on timing closure experience on complex, high‑frequency digital blocks.
• Proven record of leading design teams through at least three full‑chip tapeouts in advanced process technologies.
• Proven ability to work across teams and deliver complex design blocks with small teams.

Nice to Have

• Experience with 3D innovations
• Experience developing custom memory interfaces.
• Familiarity with memory access patterns in AI workloads.
• Experience with low‑power design techniques such as power gating, DVFS and multi‑VT optimization.
• Familiarity with DFT architectures and methods for high‑speed memory interfaces.

Compensation And Benefits

Actual compensation will be determined based on factors including, but not limited to, relevant experience, skills, qualifications, education, job responsibilities and work location.

Kepler offers a comprehensive benefits package to eligible employees, including medical, dental and vision coverage, retirement benefits, time off and additional Kepler benefits as applicable. Eligibility and benefit offerings may vary based on employment status and work location.

Equal Employment Opportunity

Kepler is an Equal Opportunity Employer. We provide equal employment opportunities to all applicants and employees and do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, or any other characteristic protected under applicable federal, state, or local law.

We believe that different backgrounds, experiences, perspectives and ideas make our team stronger and help our employees, our technology and our community thrive.

Reasonable Accommodation

Kepler is committed to providing reasonable accommodations to qualified individuals with disabilities throughout the application and hiring process. If you need a reasonable accommodation to participate in the application or interview process, please contact us at 408-365-4627 or [e-mail].

Fair Chance Hiring

Kepler will consider qualified applicants with criminal histories in accordance with applicable federal, state, and local laws, including the California Fair Chance Act. Applicants are not required to disclose criminal history before a conditional offer of employment except where otherwise permitted or required by applicable law.

Federal Contractor Notice

Kepler is a federal contractor or subcontractor and is committed to its obligations regarding equal employment opportunity. Kepler does not discriminate against qualified individuals on the basis of disability or protected veteran status and takes steps to employ and advance in employment qualified individuals with disabilities and protected veterans.

Compensation Range

Compensation Range: $270K - $310K