Principal Engineer-Design (SoC Integration and RTL/IP)

HVAC Total FM Recruitment

Chandler (AZ)

Sur place

USD 130 000 - 190 000

Plein temps

Il y a 4 jours
Soyez parmi les premiers à postuler

Une candidature complète en une minute

Un CV et une lettre de motivation personnalisés, prêts à envoyer.

Passez les filtres ATS

Résumé du poste

Microchip Technology Inc. seeks an experienced SoC Integration, RTL/IP Design, and FPGA Engineer to lead integration, RTL development, IP design, and FPGA prototyping. You will work with architecture, verification, and physical design teams to deliver high-quality hardware solutions.

Candidates should have 10+ years in ASIC/SoC design, strong SystemVerilog and AMBA protocols, and hands-on FPGA experience. This full-time, on-site role in Chandler, AZ offers growth, a collaborative culture,

Qualifications

  • Bachelor's degree required in a related engineering field.
  • 10+ years of ASIC/SoC/RTL/FPGA experience.
  • Strong SystemVerilog and AMBA expertise.
  • Experience with FPGA prototyping and IP design.

Responsabilités

  • Lead top-level and subsystem integration of processors, memories, and IP.
  • Develop synthesizable RTL and reusable peripherals and IP blocks.
  • Coordinate with architecture, verification, DFT, and physical design teams.
  • Provide technical leadership and design reviews.

Connaissances

SystemVerilog
AMBA AXI/APB
SoC integration
RTL development
FPGA prototyping

Formation

Bachelor's degree in Electrical/ Electronics Engineering, Computer Engineering, or related field

Outils

Vivado
Quartus
QuestaSim
VCS
Xcelium

Description du poste

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it's won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await!

Job Summary

The dsPIC microcontroller group is seeking an experienced SoC Integration, RTL/IP Design, and FPGA Engineer to lead SoC integration, RTL development, IP design, and FPGA prototyping activities. The candidate will work closely with architecture, verification, and physical design teams to deliver high-quality hardware solutions.

Key Responsibilities

SoC Integration Perform top-level and subsystem integration of processors, memories, peripherals, and custom IPs. Integrate IPs using proprietary bus interfaces and AMBA AXI, AHB / APB protocols. Handle clock/reset integration, interrupt routing, address mapping, and pad / pin connectivity. Resolve chip-level Lint / Synthesis / Timing issues perform CDC / RDC analysis and implement relevant fixesOwnership of post-silicon debug and ECO revisions of the chip RTL and IP Design Develop synthesizable RTL using SystemVerilog. Design reusable peripherals, controllers (for memories, ADCs, PWMs), wrappers, and power management modules. Resolve Lint / Synthesis / Timing issues; resolve CDC / RDC errors Perform RTL reviews, synthesis support, timing optimization, and design debug. Maintenance, enhancements and management of older IP Technical Leadership Collaborate with architecture, verification, DFT, physical design, firmware, and system teams. Lead design reviews, mentor junior engineers, and drive technical improvements Help with key decisions related to IP and product definition and implementation

Requirements/Qualifications

Required Skills Bachelor's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field with 10+ years of experience in ASIC/SoC design, RTL development, FPGA, or SoC integration. Strong knowledge of SystemVerilog and AMBA AXI/AHB/APB protocols. Experience with SoC integration, IP development, clock/reset architecture, and memory mapping. Hands-on experience with Vivado or Quartus, synthesis, STA, and timing closure. Familiarity with simulation tools such as QuestaSim, VCS, or Xcelium. Knowledge of CDC/RDC, RTL lint, and Python/Tcl scripting.

Preferred Qualifications

Experience with ARM/RISC-V-based SoCs, Ethernet, USB, SPI, I2C, and UART interfaces. Knowledge of low-power design, DFT integration, and Formal-based verification. Experience with FPGA synthesis, place and route, timing closure, constraint development and FPGA-based validation. Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.

Expected Deliverables

Integrated SoC/subsystem RTL and reusable IP modules. FPGA implementation and validation results. Design quality reports and integration documentation.

Role Expectation

Independently drive SoC integration, IP design, and FPGA prototyping while providing technical leadership and ensuring robust, reusable hardware designs.

Travel Time

0% - 25%

Physical Attributes

Hearing, Seeing, Talking, Works Alone, Works Around Others

Physical Requirements

Monday - Friday 8 hours/day, Inside: 100%, Sitting: 85%, Standing: 10%, walking: 5%

Equal Opportunity Statement

Microchip Technology Inc is an equal opportunity/affirmative action employer. All qualified applicants will receive consideration for employment without regard to sex, gender identity, sexual orientation, race, color, religion, national origin, disability, protected Veteran status, age, or any other characteristic protected by law. For more information on applicable equal employment regulations, please refer to the Know Your Rights: Workplace Discrimination is Illegal Poster.

Obtenez votre examen gratuit et confidentiel de votre CV.

ou faites glisser et déposez votre fichier ici.

Similar jobs

Postes similaires à comparer

Principal Engineer-Design (SoC Integration and RTL/IP)
Principal Engineer-Design (SoC Integration and RTL/IP)

Microchip Technology Inc. • Chandler (AZ)

Sur place
USD 140 000 - 190 000
Engineer I-Design
Engineer I-Design

Microchip Technology Inc. • Pennsylvania

Sur place
USD 95 000 - 140 000
Engineer I-Design
Engineer I-Design

HVAC Total FM Recruitment • Pennsylvania

Sur place
USD 75 000 - 100 000
Senior FPGA/SoC Applications Engineer
Senior FPGA/SoC Applications Engineer

Microchip Technology Inc. • Addison (TX)

Sur place
USD 91 000 - 232 000
Restricted stock units
Quarterly bonus payments
Health benefits from day one
+1
Technical Staff Engineer - Applications
Technical Staff Engineer - Applications

Microchip Technology Inc. • Hauppauge (NY)

Sur place
USD 91 000 - 232 000
Health benefits day one
ESPP program
Retirement plan
Technical Staff Engineer - Design Implementation
Technical Staff Engineer - Design Implementation

Microchip Technology Inc. • Chandler (AZ)

Sur place
USD 130 000 - 170 000
Engineer I-Design
Engineer I-Design

Microchip Technology Inc. • Allentown

Sur place
USD 70 000 - 110 000
Principal Engineer- Design (FPGA)
Principal Engineer- Design (FPGA)

Microchip Technology Inc • Chandler (AZ)

Sur place
USD 120 000 - 170 000
Engineer II - Digital ASIC Design
Engineer II - Digital ASIC Design

Microchip Technology Inc • San Jose (CA)

Sur place
USD 70 000 - 143 000
Health benefits from day one
Retirement savings plan
ESPP with 2-year lookback
Technical Staff Engineer - Design
Technical Staff Engineer - Design

Microchip Technology Inc • Chandler (AZ)

Sur place
USD 91 000 - 232 000
Competitive base pay
Restricted stock units
Quarterly bonus payments
+3