Principal SoC Design Engineer: Emulation & Co-Verification

Microchip Technology Inc.; Roseville (CA); On-site; USD 75,000 - 232,000; Full time

Benefits offered by this job

Health benefits from day one

ESPP program with 2-year look-back

Quarterly bonus payments

Job summary

Microchip Technology Inc. is seeking a Principal Design Engineer for the Architecture Co-Verification (ACOV) team.

You will collaborate with hardware designers, firmware engineers, and verification teams across the SoC development lifecycle, from architectural exploration to post-silicon validation. The role emphasizes HW/FW co-development and system-level co-verification using state-of-the-art emulators and FPGA platforms.

Qualifications

• BS/MS degree or higher in Electrical/Electronic Engineering or Computer Engineering.
• 10+ years of relevant work experience.
• Proficient Linux experience and strong programming/scripting skills (C, Python, Tcl, Bash).
• Proficient RTL coding with VHDL, Verilog, or SystemVerilog.
• Knowledge of PCIe and SAS/SATA/NVMe protocols.

Responsibilities

• Porting SoC RTL to HW emulators and FPGA platforms.
• Developing emulation-specific HW for pre-silicon verification.
• Developing test ecosystems across pre/post silicon.
• Creating FW and tests for pre-silicon verification.
• Troubleshooting complex issues in embedded multi-core real-time systems.
• Using protocol analyzers for analysis and error injection.
• Documenting verification progress and quality in defects/tools.
• Presenting technical information to small teams of engineers.

Skills

C programming

Python scripting

Verilog/SystemVerilog

VHDL

RTL design

PCIe

SAS/SATA/NVMe

Linux

ARM/MIPS/RISC-V

Education

BS/MS in Electrical/Electronic or Computer Engineering

Tools

Cadence Palladium/Protium

Test/Debug tools

Job description

Microchip Technology Inc. is seeking a Principal Design Engineer for the Architecture Co-Verification (ACOV) team.

You will collaborate with hardware designers, firmware engineers, and verification teams across the SoC development lifecycle, from architectural exploration to post-silicon validation. The role emphasizes HW/FW co-development and system-level co-verification using state-of-the-art emulators and FPGA platforms.