Principal Digital Design Engineer

Astera Labs; San Jose (CA); On-site; USD 185,000 - 230,000; Full time

Job summary

Astera Labs in San Jose, California seeks Principal Digital Design Engineers with micro-architecture and front-end circuit design experience to work on high-performance network controllers. You will contribute to RTL, synthesis, IP integration, and block-level verification for PCIe, Ualink, Esun, Ethernet, and related protocols.

The role requires 8+ years in SoC/Silicon, DFT, UVM verification, and ownership from architecture to GDS.

Qualifications

• Strong academic and technical background in electrical engineering with degree in EE.
• 8+ years’ experience in complex SoC/silicon products for Switch ASIC, Networking, Server or Storage.
• Proven ability to own architecture to GDS and drive designs to production.

Responsibilities

• Front-end circuit design including RTL, synthesis, IP integration and block-level verification.
• Owns designs from architecture to GDS and mentors others.
• Work with high-speed protocols such as PCIe, Ualink, Esun and Ethernet.

Skills

PCIe protocol

UVM verification

ASIC/SoC experience

DFT knowledge

CMOS 28nm

Troubleshooting

Education

Bachelor's degree in EE

Master's preferred

Tools

Synopsys tools

Cadence tools

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com .

Job Description

We are looking for Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.

Basic Qualifications:

• Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
• +8 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
• Authorized to work in the US and start immediately.

Required Experience:

• Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
• Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
• Experience with Synopsys and/or Cadence digital design tools/flows
• Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
• Familiarity with UVM based design verification
• Silicon bring-up and debug expertise
• Small-geometry CMOS (≤28nm) design

Preferred Experience:

• Firmware development with C-language, scripting with Python or other equivalent programming languages.
• Development/support for PCIe or Ethernet Switch products.

The base salary range is $185,000.00 USD - $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey. Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiring process or thereafter. Any information that you do provide will be recorded and maintained in an confidential file.

As set forth in Astera Labs's Equal Employment Opportunity policy, we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection. As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measure the effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categories is as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability.

A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.